CYW20736
1.5 Serial Peripheral Interface
The CYW20736 has two independent SPI interfaces. One is a master-only interface and the other can be either a master or a slave.
Each interface has a 16-byte transmit buffer and a 16-byte receive buffer. To support more flexibility for user applications, the
CYW20736 has optional I/O ports that can be configured individually and separately for each functional pin as shown in Table 3,
Table 4, and Table 5. The CYW20736 acts as an SPI master device that supports 1.8V or 3.3V SPI slaves. The CYW20736 can also
act as an SPI slave device that supports a 1.8V or 3.3V SPI master.
Table 3. CYW20736 First SPI Set (Master Mode)
Pin Name
SPI_CLK
SPI_MOSI
SPI_MISO
P24
SPI_CSa
SCL
–
SDA
–
–
–
Configured Pin Name
–
–
P26
–
P32
a. Any GPIO can be used as SPI_CS when SPI is in master mode.
Table 4. CYW20736 Second SPI Set (Master Mode)
Pin Name
SPI_CLK
SPI_MOSI
P0
SPI_MISO
SPI_CSa
P3
–
P1
P25
–
–
–
–
Configured Pin Name
P4
P24
P27
a. Any GPIO can be used as SPI_CS when SPI is in master mode.
Table 5. CYW20736 Second SPI Set (Slave Mode)
Pin Name
SPI_CLK
SPI_MOSI
SPI_MISO
SPI_CS
P2
P3
–
P0
P27
P33
–
P1
–
–
Configured Pin Name
P24
–
P25
–
P26
P32
Document Number: 002-14883 Rev. *I
Page 7 of 47
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