CYW20732A0
1.4 ADC Port
The CYW20732 contains a 16-bit ADC (effective number of bits is 10).
Additionally:
■ There are nine analog input channels in the 32-pin package
■ The following GPIOs can be used as ADC inputs:
❐ P0
❐ P1
❐ P8/P33 (select only one)
❐ P11
❐ P12
❐ P13/P28 (select only one)
❐ P14/P38 (select only one)
❐ P15
❐ P32
■ The conversion time is 10 μs.
■ There is a built-in reference with supply- or bandgap-based reference modes.
■ The maximum conversion rate is 187 kHz.
■ There is a rail-to-rail input swing.
The ADC consists of an analog ADC core that performs the actual analog-to-digital conversion and digital hardware that processes
the output of the ADC core into valid ADC output samples. Directed by the firmware, the digital hardware also controls the input
multiplexers that select the ADC input signal Vinp and the ADC reference signals Vref
.
The ADC input range is selectable by firmware control:
■ When an input range of 0–3.6V is used, the input impedance is 3 MΩ.
■ When an input range of 0–2.4V is used, the input impedance is 1.84 MΩ.
■ When an input range of 0–1.2V is used, the input impedance is 680 kΩ.
ADC modes are defined in Table 2.
Table 2. ADC Modes
Mode
ENOB (Typical)
Maximum Sampling Rate (kHz)
Latencya (μs)
0
1
2
3
4
13
5.859
11.7
171
85
21
11
5
12.6
12
46.875
93.75
187
11.5
10
a.Settling time after switching channels.
1.5 Serial Peripheral Interface
The CYW20732 has two independent SPI interfaces. One is a master-only interface and the other can be either a master or a slave.
Each interface has a 16-byte transmit buffer and a 16-byte receive buffer. To support more flexibility for user applications, the
CYW20732 has optional I/O ports that can be configured individually and separately for each functional pin as shown in Table 3,
Table 4, and Table 5. The CYW20732 acts as a SPI master device that supports 1.8V or 3.3V SPI slaves. The CYW20732 can also
act as an SPI slave device that supports a 1.8V or 3.3V SPI master.
Document Number: 002-14837 Rev. *L
Page 6 of 35
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