CYW20732A0
Figure 1. Functional Block Diagram
Muxed on GPIO
Tx RTS_N
1.2V
UART_TXD
UART_RXD
SDA/
SCL/
Rx
CTS_N
VDD_CORE
1.2V
SCK
MOSI
MISO
1.2V VDD_CORE
Domain
WDT
28 ADC
Inputs
VSS,
VDDO,
VDDC
BSC/SPI
Master
Interface
(BSC is I2C -
compaƟble)
1.2V
POR
Test
UART
Periph 320K
UART ROM
Processing
Unit
(ARM -CM3)
60K
RAM
CT ɇ ѐ
ADC
1.2V
LDO
1.425V to 3.6V
1.62V to 3.6V
3.6V
System Bus
MIA POR
32 kHz
LPCLK
Peripheral
Interface
Block
I/O Ring
Control
Registers
Volt. Trans
hclk
VDD_IO
Domain
(24 MHz to 1 MHz)
RF Control
and Data
I/O Ring Bus
Bluetooth
2.4 GHz
Radio
Baseband
Core
GPIO
Control/
Status
IR
Mod.
and
SPI
PMU
24
MHz
M/S
Learning
Registers
Power
RF I/O
T/R
Switch
Frequency
Synthesizer
32 kHz
LPCLK
WAKE
128 kHz
LPO
High Current
Driver Controls
IR
I/O
14 GPIOs
AutoCal
128 kHz
LPCLK
1.2V VDD_RF
Domain
9 ADC
Inputs
÷ 4
PWM
24 MHz
Ref Xtal
32 kHzꢀyƚĂůꢀ;ŽƉƟŽŶĂůͿꢀ
1.62V to 3.6V
VDD_IO
IoT Resources
Cypress provides a wealth of data at http://www.cypress.com/internet-things-iot to help you to select the right IoT device for your
design, and quickly and effectively integrate the device into your design. Cypress provides customer access to a wide range of
information, including technical documentation, schematic diagrams, product bill of materials, PCB layout information, and software
updates. Customers can acquire technical documentation and software from the Cypress Support Community website
(http://community.cypress.com/).
Document Number: 002-14837 Rev. *L
Page 2 of 35
CYPRESS [ CYPRESS ]
