B9846
Maximum Ratings [2]
This device contains circuitry to protect the inputs against
damage due to high-static voltages or electric fields; however,
precautions should be taken to avoid application of any
voltage higher than the maximum rated voltages to this circuit.
For proper operation, VIN and VOUT should be constrained to
the range:
Input Voltage Relative to VSS............................... VSS – 0.3V
Input Voltage Relative to VDD ..............................VDD + 0.3V
Storage Temperature ..................................–65°C to +150°C
Operating Temperature.....................................0°C to +70°C
Maximum Power Supply .................................................5.5V
VSS < (VIN or VOUT) < VDD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either VSS or VDD).
DC Parameters VDD2.5V = 2.5V + 5%, TA = 0°C to +70°C [3]
Parameter
VIL
Description
Input Low Voltage
Test Conditions
SDATA , SCLK
Min.
2.2
Typ.
Max.
Units
–
–
1.0
V
V
VIH
Input High Voltage
Input Low Voltage
VIL1
VIH1
IIH
BUFIN
1.0
Input High Voltage
Input High Current
Input Low Current
2.0
VIN = VDD, BUFIN, PD#
10
µA
µA
mA
mA
V
IIL
–TBD
IOL
Output Low Current
Output High Current
Output Low Voltage
Output High Voltage
Output Voltage Swing[6]
Output Crossing Voltage[7]
VDD = 2.375V, VOUT = 1.2V
VDD = 2.375V, VOUT = 1V
VDD = 2.375V, IOL = 12 mA
VDD = 2.375V, IOH = –12 mA
26
35
IOH
–18
–32
VOL
VOH
VOUT
VOX
IOZ
0.6
1.7
0.7
V
VDD+0.6
(VDD/2) + 0.2
10
V
(VDD/2) – 0.2
–10
VDD/2
V
High-Impedance Output
Current
VO = GND or VO = VDD
µA
IDD
Dynamic Supply Current[8] All VDD, FO = 133 MHz
Shutdown Supply Current All VDD
Input Pin Capacitance
–
–
TBD
TBD
TBD
–
mA
mA
pF
IDDS
–
CIN
5
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. Unused inputs must be held high or low to prevent them from floating.
4. Differential input signal voltage specifies the differential voltage |VTR – VCP| required for switching, where VTR is the true input level and VCP is the
complementary input level. See Figure 1. AUTHOR: NO CORRESPONDING FOOTNOTE IN THE TEXT.
5. Differential cross-point input voltage is expected to track VDD and is the voltage at which the differential signals must be crossing. AUTHOR: NO CORRE-
SPONDING FOOTNOTE IN THE TEXT.
6. For load conditions, see Figure 1.
7. The value of VOC is expected to be |VTR + VCP|/2. In case of each clock directly terminated by a 120Ω resistor. See Figure 1.
8. All outputs switching loaded with 16 pF in 60Ω environment. See Figure 1.
Document #: 38-07299 Rev. *A
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