P R E L I M I N A R Y
PIN DESCRIPTION
LOGIC SYMBOL
A20–A0
= 21 Address Inputs (Common)
21
A-1
= 2 Address Inputs (Flash)
= 16 Data Inputs/Outputs (Common)
= Chip Enable (Flash)
A20–A0
DQ15–DQ0
CE#f
A-1
SA
CE1#s
CE2s
= Chip Enable 1 (pSRAM)
= Chip Enable 2 (pSRAM)
= Output Enable (Common)
= Write Enable (Common)
= Ready/Busy Output
16 or 8
CE#f
DQ15–DQ0
OE#
CE1#s
CE2s
WE#
RY/BY#
RY/BY#
UB#s
OE#
= Upper Byte Control (pSRAM)
= Lower Byte Control (pSRAM)
WE#
LB#s
WP#/ACC
RESET#
UB#s
CIOf
= I/O Configuration (Flash)
CIOf = VIH = Word mode (x16),
CIOf = VIL = Byte mode (x8)
LB#s
RESET#
= Hardware Reset Pin, Active Low
CIOf
WP#/ACC
= Hardware Write Protect/
Acceleration Pin (Flash)
VCC
f
= Flash 3.0 volt-only single power sup-
ply (see Product Selector Guide for
speed options and voltage supply
tolerances)
VCC
VSS
NC
s
= pSRAM Power Supply
= Device Ground (Common)
= Pin Not Connected Internally
8
Am49DL32xBG
July 19, 2002