P R E L I M I N A R Y
USER BUS OPERATIONS
Read Mode
Deselecting CE (CE and RESET = V
± 0.3 V) puts
CC
the device into the I
standby mode. If the device is
CC3
The Am29LV008 has three control functions which
must be satisfied in order to obtain data at the outputs:
deselected during an Embedded Algorithm operation,
it continues to draw active power (I ) prior to entering
CC2
■ CE is the power control and should be used for de-
the standby mode, until the operation is complete.
vice selection (CE = V )
When the device is again selected (CE = V ), active
IL
IL
operations occur in accordance with the AC timing
specifications.
■ OE is the output control and should be used to gate
data to the output pins if the device is selected
(OE = V )
IL
Automatic Sleep Mode
■ WE remains at V
IH
Advanced power management features such as the
automatic sleep mode minimize Flash device energy
consumption. This is extremely important in
battery-powered applications. The Am29LV008 auto-
matically enables the low-power, automatic sleep
mode when addresses remain stable for 200 ns. Auto-
matic sleep mode is independent of the CE, WE, and
OE control signals. Typical sleep mode current draw is
200 nA (for CMOS-compatible operation). Standard
address access timings provide new data when
addresses are changed. While in sleep mode, output
data is latched and always available to the system.
Address access time (T
stable addresses to valid output data. The chip enable
) is equal to the delay from
ACC
access time (T ) is the delay from stable addresses
CE
and stable CE to valid data at the output pins. The out-
put enable access time (T ) is the delay from the fall-
ing edge of OE to valid data at the output pins
(assuming the addresses have been stable at least
OE
T
– T time).
ACC
OE
Standby Mode
The Am29LV008 is designed to accommodate low
standby power consumption by applying the following
voltages to the CE and RESET pins: I
compatible I/Os (current consumption <5 µA max.) is
enabled when a CMOS logic level ‘1’ (V ± 0.3 V) is
applied to the CE control pin with RESET = V ± 0.3
Output Disable
for CMOS
CC3
If the OE input is at a logic high level (V ), output from
IH
the device is disabled.This will cause the output pins to
be in a high impedance state.
CC
CC
V.While in the I
standby mode, the data I/O pins re-
CC3
main in the high impedance state independent of the
voltage level applied to the OE input. See the DC Char-
acteristics section for more details on Standby Modes.
8
Am29LV008T/Am29LV008B
CYPRESS [ CYPRESS ]
