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AM29F002BB-90EK 参数 Datasheet PDF下载

AM29F002BB-90EK图片预览
型号: AM29F002BB-90EK
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash, 256KX8, 90ns, PDSO32, LEAD FREE, MO-142BBD, TSOP-32]
分类和应用: 光电二极管内存集成电路
文件页数/大小: 40 页 / 1039 K
品牌: CYPRESS [ CYPRESS ]
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D A T A S H E E T  
GENERAL DESCRIPTION  
The Am29F002B Family consists of 2 Mbit, 5.0  
volt-only Flash memory devices organized as 262,144  
bytes. The Am29F002B offers the RESET# function,  
the Am29F002NB does not. The data appears on  
DQ7–DQ0. The device is offered in 32-pin PLCC and  
32-pin TSOP packages. This device is designed to be  
programmed in-system with the standard system 5.0  
Erase algorithm—an internal algorithm that automati-  
cally preprograms the array (if it is not already  
programmed) before executing the erase operation.  
During erase, the device automatically times the erase  
pulse widths and verifies proper cell margin.  
The host system can detect whether a program or  
erase operation is complete by reading the DQ7 (Data#  
Polling) and DQ6 (toggle) status bits. After a program  
or erase cycle has been completed, the device is ready  
to read array data or accept another command.  
volt V  
supply. No V is required for write or erase  
CC  
PP  
operations. The device can also be programmed in  
standard EPROM programmers.  
This device is manufactured using AMD’s 0.32 µm  
process technology, and offers all the features and ben-  
efits of the Am29F002, which was manufactured using  
0.5 µm process technology.  
The sector erase architecture allows memory sectors  
to be erased and reprogrammed without affecting the  
data contents of other sectors. The device is fully  
erased when shipped from the factory.  
The standard device offers access times of 55, 70, and  
90 ns, allowing high speed microprocessors to operate  
without wait states. To eliminate bus contention the  
device has separate chip enable (CE#), write enable  
(WE#) and output enable (OE#) controls.  
Hardware data protection measures include a low VCC  
detector that automatically inhibits write operations during  
power transitions. The hardware sector protection  
feature disables both program and erase operations in  
any combination the sectors of memory. This can be  
achieved via programming equipment.  
The device requires only a single 5.0 volt power  
supply for both read and write functions. Internally  
generated and regulated voltages are provided for the  
program and erase operations.  
The Erase Suspend feature enables the user to put  
erase on hold for any period of time to read data from,  
or program data to, any sector that is not selected for  
eraure. True background erase can thus be achieved.  
The device is entirely command set compatible with the  
JEDEC single-power-supply Flash standard. Com-  
mands are written to the command register using  
standard microprocessor write timings. Register con-  
tents serve as input to an internal state-machine that  
controls the erase and programming circuitry. Write  
cycles also internally latch addresses and data needed  
for the programming and erase operations. Reading  
data out of the device is similar to reading from other  
Flash or EPROM devices.  
The hardware RESET# pin terminates any operation  
in progress and resets the internal state machine to  
reading array data. The RESET# pin may be tied to the  
system reset circuitry. A system reset would thus also  
reset the device, enabling the system microprocessor  
to read the boot-up firmware from the Flash memory.  
(This feature is not available on the Am29F002NB.)  
The system can place the device into the standby mode.  
Power consumption is greatly reduced in this mode.  
Device programming occurs by eecuting the program  
command sequence. This initiates the Embedded  
Program algorithm—an internal algorithm that auto-  
matically times the program pulse widths and verifies  
proper cell margin.  
AMD’s Flash technology combines years of Flash  
memory manufacturing experience to produce the  
highest levels of quality, reliability and cost effectiveness.  
The device electrically erases all bits within a sector  
simultaneously via Fowler-Nordheim tunneling. The  
data is programmed using hot electron injection.  
Device erasure occurs by executing the erase  
command sequence. This initiates the Embedded  
2
Am29F002B/Am29F002NB  
21527D8 November 17, 2009  
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