D A T A S H E E T
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state
machine. The state machine outputs dictate the func-
tion of the device. The appropriate device bus
operations table lists the inputs and control levels
required, and the resulting output. The following sub-
sections describe each of these operations in further
detail.
Table 1. Am29F002B/Am29F002NB Device Bus Operations
RESET#
Operation
CE#
OE# WE#
(n/a Am29F002NB)
A0–A17
DQ0–DQ7
DOUT
Read
Write
L
L
H
X
X
H
X
H
L
H
H
H
H
H
L
AIN
AIN
X
L
DIN
CMOS Standby
VCC 0.5 V
X
X
H
X
High-Z
High-Z
High-Z
High-Z
TTL Standby
H
L
X
Output Disable
X
Reset (n/a on Am29F002NB)
X
X
Temporary Sector Unprotect
(See Note)
X
X
X
VID
X
X
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 0.ꢀ V, X = Don’t Care, DIN = Data In, DOUT = Data Out, AIN = Address In
Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information. This function requires
the RESET# pin and is therefore not available on the Am29F002NB device.
sectors of memory), the system must drive WE# and
Requirements for Reading Array Data
To read array data from the outputs, the system must
CE# to V , and OE# to V .
IL
IH
drive the CE# and OE# pins to V . CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables
indicate the address space that each sector occupies.
A “sector address” consists of the address bits required
to uniquely select a sector. See the Command Defini-
tions section for details on erasing a sector or the entire
chip, or suspending/resuming the erase operation.
IL
should remain at V .
IH
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
After the system writes the autoselect command
sequence, the device enters the autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the “Autoselect Mode” and
Autoselect Command Sequence sections for more
information.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
I
in the DC Characteristics table represents the
CC2
active current specification for the write mode. The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
the timing waveforms. I
in the DC Characteristics
CC1
table represents the active current specification for
reading array data.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “Write Operation
8
Am29F002B/Am29F002NB
21527D8 November 17, 2009
CYPRESS [ CYPRESS ]
