CY7C372i
Switching Characteristics Over the Operating Range [14]
7C372i-83
7C372i-66
7C372i-125 7C372i-100 7C372iL-83 7C372iL-66
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Unit
Combinatorial Mode Parameters
tPD
Input to Combinatorial Output[1]
10
13
12
15
15
18
20
22
ns
ns
tPDL
Input to Output Through Transparent Input or
Output Latch[1]
tPDLL
Input to Output Through Transparent Input and
Output Latches[1]
15
16
19
24
ns
tEA
tER
Input to Output Enable[1]
14
14
16
16
19
19
24
24
ns
ns
Input to Output Disable
Input Registered/Latched Mode Parameters
tWL
tWH
tIS
Clock or Latch Enable Input LOW Time[9]
Clock or Latch Enable Input HIGH Time[9]
Input Register or Latch Set-Up Time
Input Register or Latch Hold Time
3
3
2
2
3
3
2
2
4
4
3
3
5
5
4
4
ns
ns
ns
ns
ns
tIH
tICO
Input Register Clock or Latch Enable to
Combinatorial Output[1]
14
16
16
18
19
21
24
26
tICOL
Input Register Clock or Latch Enable to Output
Through Transparent Output Latch[1]
ns
Output Registered/Latched Mode Parameters
tCO
Clock or Latch Enable to Output[1]
tS Set-Up Time from Input to Clock or Latch Enable 5.5
6.5
14
6.5
16
8
10
24
ns
ns
ns
ns
6
0
8
0
10
0
tH
Register or Latch Data Hold Time
0
tCO2
Output Clock or Latch Enable to Output Delay
(Through Memory Array)[1]
19
tSCS
tSL
Output Clock or Latch Enable to Output Clock
or Latch Enable (Through Memory Array)
8
10
0
10
12
0
12
15
0
15
20
0
ns
ns
Set-Up Time from Input Through Transparent
Latch to Output Register Clock or Latch Enable
tHL
Hold Time for Input Through Transparent Latch
from Output Register Clock or Latch Enable
ns
fMAX1
Maximum Frequency with Internal Feedback in 125
Output Registered Mode (Least of 1/tSCS
100
83
66
MHz
,
[9]
1/(tS + tH), or 1/tCO
)
fMAX2
Maximum Frequency Data Path in Output
153.8
153.8
125
100
MHz
Registered/Latched Mode (Lesser of 1/(tWL
+
[9]
tWH), 1/(tS + tH), or 1/tCO
)
fMAX3
Maximum Frequency with External Feedback 83.3
(Lesser of 1/(tCO + tS) and 1/(tWL + tWH))[9]
80
0
62.5
0
50
0
MHz
ns
tOH-tIH
37x
Output Data Stable from Output clock Minus
Input Register Hold Time for 7C37x[9, 15]
0
Pipelined Mode Parameters
tICS Input Register Clock to Output Register Clock
fMAX4
8
10
12
15
ns
Maximum Frequency in Pipelined Mode (Least 125
100
83.3
66.6
MHz
of 1/(tCO + tIS), 1/tICS, 1/(tWL + tWH), 1/(tIS + tIH), or
[9]
1/tSCS
)
Notes:
14. All AC parameters are measured with 16 outputs switching and 35-pF AC Test Load.
15. This specification is intended to guarantee interface compatibility of the other members of the CY7C370i family with the CY7C372i. This specification is met for
the devices operating at the same ambient temperature and at the same power supply voltage.
Document #: 38-03033 Rev. *A
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