CY7C199
[3, 7]
Switching Characteristics Over the Operating Range (-8, -10, -12, -15)
7C199-8
7C199-10
7C199-12
Min. Max.
7C199-15
Min. Max.
Parameter
Read Cycle
tRC
Description
Min.
Max.
Min.
10
3
Max.
Unit
Read Cycle Time
8
3
12
3
15
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[8]
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[8]
CE HIGH to High-Z[8,9]
CE LOW to Power-up
CE HIGH to Power-down
8
10
12
15
tOHA
tACE
8
10
5
12
5
15
7
tDOE
4.5
tLZOE
tHZOE
tLZCE
tHZCE
tPU
0
3
0
0
3
0
0
3
0
0
3
0
5
4
8
5
5
5
5
7
7
tPD
10
12
15
Write Cycle[10, 11]
tWC
tSCE
tAW
Write Cycle Time
8
7
7
0
0
7
5
0
10
7
12
9
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE LOW to Write End
Address Set-up to Write End
Address Hold from Write End
Address Set-up to Write Start
WE Pulse Width
7
9
tHA
0
0
tSA
0
0
0
tPWE
tSD
7
8
9
Data Set-up to Write End
Data Hold from Write End
WE LOW to High-Z[9]
5
8
9
tHD
0
0
0
tHZWE
tLZWE
5
6
7
7
WE HIGH to Low-Z[8]
3
3
3
3
Switching Characteristics Over the Operating Range (-20, -25, -35, -45)[3, 7]
7C199-20 7C199-25
Min. Max.
7C199-35
7C199-45
Parameter
Read Cycle
tRC
Description
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
20
3
25
3
35
3
45
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tAA
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low-Z[8]
OE HIGH to High-Z[8, 9]
CE LOW to Low-Z[8]
20
25
35
45
tOHA
tACE
20
9
25
10
35
16
45
16
tDOE
tLZOE
0
3
0
0
3
0
0
3
0
0
3
0
tHZOE
tLZCE
tHZCE
tPU
9
9
11
11
15
15
15
15
CE HIGH to High-Z[8, 9]
CE LOW to Power-up
Shaded area contains advance information.
Notes:
7. Test conditions assume signal transition time of 3 ns or less for -12 and -15 speeds and 5 ns or less for -20 and slower speeds, timing reference levels of 1.5V,
input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
10. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
11. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
Document #: 38-05160 Rev. *A
Page 4 of 13
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