CY7C187
Switching Waveforms
Read Cycle No. 2[10, 12]
t
RC
CE
t
ACE
t
t
HZCE
LZCE
HIGH
IMPEDANCE
HIGH IMPEDANCE
DATA OUT
DATA VALID
t
PD
t
PU
V
CC
ICC
SUPPLY
CURRENT
50%
50%
ISB
C187–7
Write Cycle No. 1 (WE Controlled)[11]
t
WC
ADDRESS
t
SCE
CE
t
t
HA
AW
t
SA
t
PWE
WE
t
t
HD
SD
DATA IN
DATA VALID
t
t
LZWE
HZWE
HIGH IMPEDANCE
DATA OUT
DATA UNDEFINED
C187–8
Write Cycle No. 2 (CE Controlled)[11, 13]
t
WC
ADDRESS
t
SA
t
SCE
CE
t
t
HA
AW
t
PWE
WE
t
t
HD
SD
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
C187–9
Notes:
12. Address valid prior to or coincident with CE transition LOW.
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05044 Rev. **
Page 5 of 9
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