CY7C185
Switching Waveforms (continued)
rite Cycle No. 2 (CE Controlled)[13,14,15]
t
WC
ADDRESS
t
t
CE
1
SCE1
t
SA
SCE2
CE
2
t
t
HA
AW
WE
t
t
HD
SD
DATA VALID
DATA I/O
IN
Write Cycle No. 3 (WE Controlled, OE LOW)[13,14,15,16]
t
WC
ADDRESS
t
CE
SCE1
1
t
CE
SCE2
2
t
t
HA
AW
t
SA
WE
t
t
HD
SD
DATA I/O
DATA VALID
NOTE 14
IN
t
t
LZWE
HZWE
Notes:
15. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD
.
16. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in a high-impedance state.
Document #: 38-05043 Rev. *A
Page 6 of 11
CYPRESS [ CYPRESS ]
