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7C1041AV33-10 参数 Datasheet PDF下载

7C1041AV33-10图片预览
型号: 7C1041AV33-10
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ×16静态RAM [256K x 16 Static RAM]
分类和应用:
文件页数/大小: 9 页 / 142 K
品牌: CYPRESS [ CYPRESS ]
 浏览型号7C1041AV33-10的Datasheet PDF文件第1页浏览型号7C1041AV33-10的Datasheet PDF文件第2页浏览型号7C1041AV33-10的Datasheet PDF文件第3页浏览型号7C1041AV33-10的Datasheet PDF文件第5页浏览型号7C1041AV33-10的Datasheet PDF文件第6页浏览型号7C1041AV33-10的Datasheet PDF文件第7页浏览型号7C1041AV33-10的Datasheet PDF文件第8页浏览型号7C1041AV33-10的Datasheet PDF文件第9页  
CY7C1041AV33/  
GVT73256A16  
PRELIMINARY  
Switching Characteristics[5] Over the Operating Range  
7C1041AV33-10/  
GVT73256A16-10  
7C1041AV33-12/  
GVT73256A16-12  
Parameter  
Description  
Min.  
Max.  
Min.  
Max.  
Unit  
READ CYCLE  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
READ Cycle Time  
10  
12  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address Access Time  
10  
10  
102  
12  
AA  
Chip Enable Access Time  
ACE  
OH  
Output Hold from Address Change  
3
3
3
3
[6, 7]  
Chip Enable to Output in Low-Z  
LZCE  
HZCE  
AOE  
LZOE  
HZOE  
ABE  
LZBE  
HZBE  
PU  
[6, 7, 8]  
Chip Disable to Output in High-Z  
Output Enable Access Time  
Output Enable to Output in Low-Z  
Output Enable to Output in High-Z  
Byte Enable Access Time  
5
5
6
6
0
0
[6, 8]  
5
5
6
6
[6, 7]  
Byte Enable to Output in Low-Z  
0
0
0
0
[6, 7, 8]  
Byte Disable to Output in High-Z  
5
6
[6]  
Chip Enable to Power-up Time  
[6]  
Chip Disable to Power-down Time  
10  
12  
PD  
WRITE CYCLE  
t
t
t
t
t
t
t
t
t
t
t
t
WRITE Cycle Time  
10  
8
12  
8
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
Chip Enable to End of Write  
Address Valid to End of Write, with OE HIGH  
Address Set-up Time  
CW  
AW  
8
8
0
0
AS  
Address Hold from End of Write  
WRITE Pulse Width  
0
0
AH  
10  
8
10  
8
WP2  
WP1  
DS  
WRITE Pulse Width, with OE HIGH  
Data Set-up Time  
5
6
Data Hold Time  
0
0
DH  
[6, 7]  
Write Disable to Output in Low-Z  
3
4
LZWE  
HZWE  
BW  
[6, 7, 8]  
Write Enable to Output in High-Z  
5
6
Byte Enable to End of Write  
8
8
Data Retention Characteristics Over the Operating Range (For L version only)  
Parameter  
Description  
Conditions  
Min. Typ. Max. Unit  
V
V
for Data Retention  
CC  
2.0  
V
DR  
[9]  
I
Data Retention Current  
CE > V 0.2V;  
all other inputs < V + 0.2 or  
V
V
= 2V  
= 3V  
0.2  
0.3  
1.6  
2.4  
mA  
mA  
CCDR  
CC  
CC  
CC  
SS  
>V 0.2; all inputs static; f = 0  
CC  
[6]  
t
t
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
ns  
ns  
CDR  
[6, 10]  
t
R
RC  
Notes:  
7. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE  
.
8. Output loading is specified with CL=5 pF as in AC Test Loads. Transition is measured ±500mV from steady state voltage.  
9. Capacitance derating applies to capacitance different from the load capacitance shown in AC Test Loads.  
10. tRC = Read Cycle Time.  
4