CY7C225A
AC Test Loads and Waveforms[4]
R1 250Ω
R1 250Ω
5V
5V
ALL INPUT PULSES
OUTPUT
OUTPUT
3.0V
GND
90%
10%
90%
10%
50 pF
5pF
R2
R2
167Ω
167Ω
< 5 ns
< 5 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
(a) NormalLoad
(b) HighZ Load
Equivalent to:
THÉVENIN EQUIVALENT
100Ω
OUTPUT
2.0V
the subsequent positive clock edge will return the output to the
active state if E is LOW. Following a positive clock edge, the
address and synchronous enable inputs are free to change
since no change in the output will occur until the next
LOW-to-HIGH transition of the clock. This unique feature
allows the CY7C225A decoders and sense amplifiers to
access the next location while previously addressed data
remains stable on the outputs.
Operating Modes
The CY7C225A incorporates a D-type, master-slave register
on chip, reducing the cost and size of pipelined micropro-
grammed systems and applications where accessed PROM
data is stored temporarily in a register. Additional flexibility is
provided with synchronous (ES) and asynchronous (E) output
enables and CLEAR and PRESET inputs.
Upon power-up, the synchronous enable (ES) flip-flop will be
in the set condition causing the outputs (O0−O7) to be in the
OFF or high-impedance state. Data is read by applying the
memory location to the address inputs (A0−A8) and a logic
LOW to the enable (ES) input. The stored data is accessed and
loaded into the master flip-flops of the data register during the
address set-up time. At the next LOW-to-HIGH transition of the
clock (CP), data is transferred to the slave flip-flops, which
drive the output buffers, and the accessed data will appear at
the outputs (O0−O7) provided the asynchronous enable (E) is
also LOW.
System timing is simplified in that the on-chip edge-triggered
register allows the PROM clock to be derived directly from the
system clock without introducing race conditions. The on-chip
register timing requirements are similar to those of discrete
registers available in the market.
The CY7C225A has buffered asynchronous CLEAR and
PRESET inputs. Applying a LOW to the PRESET input causes
an immediate load of all ones into the master and slave
flip-flops of the register, independent of all other inputs,
including the clock (CP). Applying a LOW to the CLEAR input,
resets the flip-flops to all zeros. The initialize data will appear
at the device outputs after the outputs are enabled by bringing
the asynchronous enable (E) LOW.
The outputs may be disabled at any time by switching the
asynchronous enable (E) to a logic HIGH, and may be
returned to the active state by switching the enable to a logic
LOW.
When power is applied, the (internal) synchronous enable
flip-flop will be in a state such that the outputs will be in the
high-impedance state. In order to enable the outputs, a clock
must occur and the ES input pin must be LOW at least a set-up
time prior to the clock LOW-to-HIGH transition. The E input
may then be used to enable the outputs.
Regardless of the condition of E, the outputs will go to the OFF
or high-impedance state upon the next positive clock edge
after the synchronous enable (ES) input is switched to a HIGH
level. If the synchronous enable pin is switched to a logic LOW,
Document #: 38-04001 Rev. *B
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