CY7C261
CY7C263/CY7C264
Switching Waveforms[4]
t
t
PU
PD
V
CC
SUPPLY
CURRENT
50%
50%
A -
0
A
12
ADDRESS
CS
t
AA
t
t
ACS
HZCS
O -
0
O
7
Erasure Characteristics
Operating Modes
Wavelengths of light less than 4000 angstroms begin to erase
the devices in the windowed package. For this reason, an
opaque label should be placed over the window if the PROM
is exposed to sunlight or fluorescent lighting for extended
periods of time.
Read
Read is the normal operating mode for programmed device. In
this mode, all signals are normal TTL levels. The PROM is
addressed with a 13-bit field, a chip select, (active LOW), is
applied to the CS pin, and the contents of the addressed location
appear on the data out pins.
The recommended dose of ultraviolet light for erasure is a
wavelength of 2537 angstroms for a minimum dose (UV
intensity multiplied by exposure time) of 25 Wsec/cm2. For an
ultraviolet lamp with a 12 mW/cm2 power rating, the exposure time
would be approximately 35 minutes. The 7C261 or 7C263
needs to be within 1 inch of the lamp during erasure.
Permanent damage may result if the PROM is exposed to
high-intensity UV light for an extended period of time. 7258
Wsec/cm2 is the recommended maximum dosage.
Program, Program Inhibit, Program Verify
These modes are entered by placing a high voltage VPP on pin
19, with pins 18 and 20 set to VILP. In this state, pin 21 becomes a
latch signal, allowing the upper 5 address bits to be latched into an
onboard register, pin 22 becomes an active LOW program (PGM)
signal and pin 23 becomes an active LOW verify (VFY) signal. Pins
22 and 23 should never be active LOW at the same time. The
PROGRAM mode exists when PGM is LOW, and VFY is HIGH. The
verify mode exists when the reverse is true, PGM HIGH and VFY
LOW and the program inhibit mode is entered with both PGM and
VFY HIGH. Program inhibit is specifically provided to allow data to be
placed on and removed from the data pins without conflict
Table 1. Mode Selection
Pin Function[6, 7]
Read or Output Disable
Program
A12
NA
A11
VPP
A11
A10
LATCH
A10
A9
PGM
A9
A8
VFY
A8
CS
CS
O7–O0
D7–D0
O7–O0
High Z
D7–D0
High Z
O7–O0
O7–O0
Mode
Read
A12
A12
VILP
VILP
VILP
VILP
VIL
Output Disable
Program
A11
A10
A9
A8
VIH
VPP
VPP
VPP
VPP
VILP
VILP
VIHP
VIHP
VIHP
VIHP
VIHP
VILP
VILP
VILP
VILP
VILP
VILP
Program Inhibit
Program Verify
Blank Check
VILP
VILP
VILP
Notes:
6. X = “don’t care” but not to exceed VCC ±5%.
7. Addresses A8-A12 must be latched through lines A0-A4 in programming modes.
Document #: 38-04010 Rev. *B
Page 5 of 14
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