CY7C265
Table 1. Mode Selection
Pin Function
Read or Output Disable
Other
A12
A12
A12
A12
A12
A12
A12
A12
VIHP
VILP
A12
A11
A11
A11
A10–A7
A10–A7
A10–A7
A10–A7
A10–A7
A10–A7
A10–A7
A10–A7
A10–A7
A10–A7
A10 – A7
A6
A6
A5
A5
A4–A3
A2
A2
Mode
A4–A3
A4–A3
A4–A3
A4–A3
A4–A3
A4–A3
A4–A3
A4–A3
A4–A3
A4–A3
Asynchronous Enable Read
Synchronous Enable Read
Asynchronous Initialization Read
Program Memory
A6
A5
A2
A11
A6
A5
A2
A11
A6
A5
A2
A11
A6
A5
A2
Program Verify
A11
A6
A5
A2
Program Inhibit
A11
A6
A5
A2
Program Synchronous Enable
Program Initialize
VIHP
VIHP
VILP
VIHP
VIHP
VIHP
VPP
VPP
VPP
VIHP
VILP
VILP
Program Initial Byte
Pin Function
Read or Output Disable
Other
A1
A1
A0
GND
CLK
GND
E, I
O7–O0
D7–D0
O7–O0
O7–O0
O7–O0
D7–D0
O7–O0
High Z
D7–D0
D7–D0
D7–D0
Mode
A0
A0
PGM
GND
GND
GND
VILP
VIHP
VIHP
VILP
VILP
VILP
CLK
VIL
VFY
GND
GND
GND
VIHP
VILP
VPP
VIL
Asynchronous Enable Read
Synchronous Enable Read
Asynchronous Initialization Read
Program Memory
A1
A1
A0
VIL/VIH
VIL
VIL
A1
A0
VIL
A1
A0
VILP
VILP
VILP
VILP
VILP
VILP
VPP
VPP
VPP
VPP
VPP
VPP
Program Verify
A1
A0
Program Inhibit
A1
A0
VIHP
VIHP
VIHP
VIHP
Program Synchronous Enable
Program Initialize
VPP
VPP
VPP
VILP
VILP
VIHP
Program Initial Byte
DIP/Flatpack
LCC/PLCC (Opaque Only)
1
28
27
26
A
7
A
6
A
5
V
CC
2
3
A
8
3
2 1 28 27
4
26
25
A
9
A
A
A
V
NA
VFY
A
10
11
12
5
6
7
8
9
3
A
4
25
24
23
22
21
4
A
A
A
10
11
12
24
23
22
21
20
19
A
2
A
A
5
3
PGM
CLK
6
PP
2
A
1
PGM
CLK
7
8
V
PP
A
0
10
11
NA
D
0
D
7
A
1
9
20
19
18
17
16
VFY
1314151617 18
12
A
0
10
11
12
13
D
7
D
6
D
0
D
1
D
5
D
2
D
4
GND
D
3
14
15
Figure 1. Programming Pinout
programming information, including a listing of software pack-
ages, please see the PROM Programming Information located
at the end of this section. Programming algorithms can be ob-
tained from any Cypress representative.
Programming Information
Programming support is available from Cypress as well as
from a number of third-party software vendors. For detailed
Document #: 38-04012 Rev. **
Page 6 of 13
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