Delta39K™ ISR™
CPLD Family
PLL and Clock MUX
GCLK[3:0]
GCTL[3:0]
4
4
I/O Bank 7
I/O Bank 6
GCLK[3:0]
4
4
4
4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 7
LB 6
LB 5
LB 4
LB 0
LB 7
LB 6
LB 6
LB 5
LB 4
LB 1
LB 2
LB 3
LB 1
LB 2
LB 3
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
PIM
PIM
PIM
PIM
LB 5
LB 4
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
GCLK[3:0]
4
4
4
4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
PIM
PIM
PIM
PIM
LB 5
LB 4
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
GCLK[3:0]
4
4
4
4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
LB 5
LB 4
LB 0
LB 1
LB 2
LB 3
LB 7
LB 6
Channel
RAM
Channel
RAM
Channel
RAM
Channel
RAM
PIM
PIM
PIM
PIM
LB 5
LB 4
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
Cluster
RAM
I/O Bank 2
I/O Bank 3
Figure 1. Delta39K100 Block Diagram (Three Rows × Four Columns) with I/O Bank Structure
The architecture is based on Logic Block Clusters (LBC) that
General Description
are connected by Horizontal and Vertical (H and V) routing
channels. Each LBC features eight individual Logic Blocks
(LB) and two cluster memory blocks. Adjacent to each LBC is
a channel memory block, which can be accessed directly from
the I/O pins. Both types of memory blocks are highly config-
urable and can be cascaded in width and depth. See Figure 1
for a block diagram of the Delta39K architecture.
The Delta39K family, based on a 0.18-mm, six-layer metal
CMOS logic process, offers a wide range of high-density
solutions at unparalleled system performance. The Delta39K
family is designed to combine the high speed, predictable
timing, and ease of use of CPLDs with the high densities and
low power of FPGAs. With devices ranging from 30,000 to
200,000 usable gates, the family features devices ten times
the size of previously available CPLDs. Even at these large
densities, the Delta39K family is fast enough to implement a
fully synthesizable 64-bit, 66-MHz PCI core.
All the members of the Delta39K family have Cypress’s highly
regarded In-System Reprogrammability (ISR) feature, which
simplifies both design and manufacturing flows, thereby
reducing costs. The ISR feature provides the ability to recon-
Document #: 38-03039 Rev. *H
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