CCLD-034 5×7mm SMD
LVDS Clock Oscillator
CCLD-034 Model
5×7 mm SMD, 3.3V, LVDS
Crystek Part Number Guide
CCLD - 034 X - 50 - 250.000
Standard Frequencies
#1
#2
#3
#4
#5
(±50ppm, 0/70°C)
Stability Indicator
#1 Crystek LVDS Osc.
#2 Model 034
200.000 MHz
212.500 MHz
250.000 MHz
Blank
50
± 100ppm
#3 Temp Range: Blank = 0/70°C, M = -20/70°C, X = -40/85°C
#4 Stability: (see Table 1)
#5 Frequency in MHz: 3 or 6 decimal places
±
±
±
50ppm
25ppm
20ppm
25
20*
Example:
*not available in -40/85
CCLD-034X-50-311.040
3.3V, -40/85°C, ±50ppm, 250.000 MHz
Table 1
RECOMMENDED REFLOW SOLDERING PROFILE
Ramp-Up
3°C/Sec Max.
Critical
Temperature Zone
Mechanical:
260°C
Ramp-Down
6°C/Sec.
Shock: MIL-STD-883, Method 2002, Condition B
Solderability: MIL-STD-883, Method 2003
217°C
200°C
150°C
Vibration: MIL-STD-883, Method 2007, Condition A
Solvent Resistance: MIL-STD-202, Method 215
Resistance to Soldering Heat: MIL-STD-202, Method 210, Condition I or J
Environmental:
Preheat
Thermal Shock: MIL-STD-883, Method 1011, Condition A
Moisture Resistance: MIL-STD-883, Method 1004
90 Secs. Max.
180 Secs. Max.
8 Minutes Max.
260°C for
10 Secs. Max.
NOTE: Reflow Profile with 240°C peak also acceptable.
0.274 ±0.007
(6.96 ±0.18)
Dimensions inches (mm)
Tristate Function
All dimensions are Max unless otherwise specified.
Part Number
Frequency
DC Lot Code
Function pin 1
Output pin
0.193 ±0.007
(4.90 ±0.18)
Open or N/C
"1" level 0.7×Vdd Min
"0" level 0.3×Vdd Max
Active
Active
High Z
0.071
(1.80)
Denotes pad 1
SUGGESTED PAD LAYOUT
via to
ground
0.01µF
PIN
Connection
Enable/Disable
0.055 Typ
(1.40 Typ)
0.071 SQ
(1.80)
1
2
3
4
5
6
0.045 ±0.008
(1.14 ±0.20)
N/C
GND
Output
#1
#6
#2
#5
#3
#4
0.148
(3.75)
Comp Output
Vcc
0.100
(2.54)
0.200
(5.08)
0.200
(5.08)
Rev: K
0.01uF Bypass Capacitor Recommended
Date: 29-Sep-2014
Page 3 of 3
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CORPORATION
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