CPC7583
Table 12. Truth Table for the CPC7583BA and CPC7583BB
INring
INtestin
INtestout
TSD
TESTin
Switches
Break
Switches
RingTest
Switches
Ring
Switches
TESTout
Switches
0V
0V
0V
5V
5V
0V
5V
5V
0V
0V
5V
0V
5V
5V
0V
5V
0V
5V
0V
0V
0V
5V
5V
5V
5V/Float1
5V/Float1
5V/Float1
5V/Float1
5V/Float1
5V/Float1
5V/Float1
5V/Float1
0V2
Off
Off
On
Off
Off
On
Off
Off
Off
On
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
Off
Off
Off
On
Off
Off
Off
Off
Off
Off3
On4
Off5
Off6
Off7
On8
Off9
Off9
Off9
Don’t
Care
1
Don’t
Care
Don’t
Care
If TSD = 5V, the thermal shutdown mechanism is disabled.
If TSD if floating, the thermal shutdown mechanism is active.
Forcing TSD to ground overrides the logic input pins and forces an all off state.
Idle/Talk State.
2
3
4
5
6
7
8
TESTout state.
TESTin state.
Power Ringing State.
Ringing generator test state.
Simultaneous TESTout and TESTin state.
All OFF State
9
A parallel in/parallel out data latch is integrated into the CPC7583. Operation of the data latch is controlled by the logic level input pin
LATCH. The data input to the latch is the INPUT pin of the CPC7583 and the output of the data latch is an internal node used for state
control.
When the LATCH control pin is at logic 0, the data latch is transparent and data control signals flow directly from INPUT, through the data
latch to state control. Any changes in INPUT will be reflected in the state of the switches.
When the LATCH control pin is at logic 1, the data latch is active; the CPC7583 will no longer react to changes at the INPUT control pin. The
state of the switches is now latched; that is, the state of the switches will remain as they were when the LATCH input transitioned from logic
0 to logic 1. The switches will not respond to changes in INPUT as long as LATCH is held high.
Note that the Tsd input is not tied to the data latch. Tsd is not affected by the LATCH input. Tsd input will override state control via INPUT
and LATCH.
Rev. E
8
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