MXED401
Data Input Procedure
A data synchronization bit is entered into the TOKEN bit shift register via the SRIN (or SLIN) on a
rising edge of SCLK. The token bit travels along the complete shift register path in order to control
data latching. The internal logic is shown below. Notice the use of the SCLK divider. SCLK frequency
is halved inside the IC to keep the current consumption to a minimum. The shift logic modifies the
input signals in a manner that requires input data (DAT5:0) to follow the SRIN synchronization bit by
2 SCLK rising edges. Initialization of the system is accomplished via the RB input pin. The 6-bit data
word is passed through the output register when pin LAT is LOW. When pin LAT is HIGH data is
latched in the output storage register.
The inputs SHR and SEL200 are set by the user to control SHift-Right (versus shift left) operation
and SELect 200 output configuration (versus 192 output configuration.). When SEL200 is LOW the
user ignores the output pads near the edge of the die. That is, ignore outputs O0-O3 and O196-
O199, use only outputs O4-O195. When SHR is HIGH data is loaded first into the lower number
outputs first and completes the load at the higher numbered outputs. For example, with SHR high
and SEL200 low the input data will load into register O4 first and complete the cycle by loading O195
on the last clock edge.
FIGURE 9 - INTERNAL LOGIC DETAILS FOR DATA PATH
www.clare.com
14580
8
CLARE [ CLARE ]
