Electrical Characteristics: continued
TEST CONDITIONS MIN
PARAMETER
TYP
MAX
UNIT
■ WATCHDOG Input
Threshold
HIGH
1.4
1.3
2.0
V
V
LOW
0.8
25
-10
5
Hysteresis
100
0
mV
µA
µs
Input Current
Pulse Width
0 < WDI < 6V
+10
50% WDI falling edge to
50% WDI rising edge and
50% WDI rising edge to 50%
WDI falling edge (see Figure 1)
■ WAKE UP Output
WAKE UP Period
see Figure 1a
see Figure 1c
30
40
15
40
50
20
50
60
25
ms
%
WAKE UP Duty Cycle nominal
RESET
RESET
rising edge to
HIGH to WAKE UP
50%
ms
Rising Delay Time
50% WAKE UP edge
(see Figure 1)
WAKE UP Response
to Watchdog Input
50% WDI falling edge to
50% WAKE UP falling edge
2
2
10
10
µs
µs
RESET
falling edge to
WAKE UP Response
50%
50% WAKE UP falling edge
OUT = 5V®4.5V
RESET
to
V
Output
LOW
IOUT = 25µA(sinking)
IOUT = 25µA(sourcing)
0.2
4.2
0.8
5.1
V
V
HIGH
3.8
Current Limit
WAKE UP = 5V
WAKE UP = 0V
0.025
.05
1.00
7.00
3.50
mA
mA
Package Lead Description
Package Lead #
16 L PDIP
Lead Symbol
Function
7L TO-220 &
7L D2PAK
2
16L SOIC
(internally fused) (internally fused)
9
9
VIN
Supply voltage to the IC.
3
11
11
WDI
CMOS/TTL compatible input lead. The watchdog function
monitors the falling edge of the incoming signal.
4
7
4,5,12,13
16
4,5,6,12,13
16
Gnd
Ground Connection
Delay
Input lead from timing capacitor for RESET and WAKE UP
signal.
6
15
14
15
14
RESET
CMOS/TTL compatible output lead RESET goes low when-
ever VOUT drops by more than 6% from nominal, or during
the absence of a correct watchdog signal.
5
1
WAKE UP CMOS/TTL compatible output consisting of a continuously
generated signal used to WAKE UP the microprocessor from
sleep mode.
8
7
8
7
VOUT
Regulated output voltage 5V ± 2%.
Sense
Kelvin connection which allows remote sensing of the output
voltage for improved regulation. If remote sensing is not
required, connect to VOUT
.
3
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
