Electrical Characteristics: TA = 0¡C to 70¡C, 0¡C ² TJ ² 125¡C, 6V ² VIN ² 26V, IOUT = 100µA to 100mA,
C2 = 47µF (ESR < 8½), CDelay = 0.1µF (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
■ Watchdog Input
Threshold
HIGH
1.4
1.3
2.0
V
V
LOW
0.8
25
-10
5
Hysteresis
100
0
mV
µA
µs
Input Current
Pulse Width
0 < WDI < 6V
+10
50% WDI falling edge to
50% WDI rising edge and
50% WDI rising edge to 50%
WDI falling edge (see Figure 1)
■ Wake Up Output
Wake Up Period
see Figure 1a
see Figure 1c
30
40
15
40
50
20
50
60
25
ms
%
Wake Up Duty Cycle nominal
RESET
RESET
rising edge to
HIGH to Wake Up
50%
ms
Rising Delay Time
50% Wake Up edge
(see Figure 1)
Wake Up Response
to Watchdog Input
50% WDI falling edge to
50% Wake Up falling edge
2
2
10
10
µs
µs
RESET
falling edge to
Wake Up Response
50%
50% Wake Up falling edge
OUT = 5V®4.5V
RESET
to
V
Output
LOW
IOUT = 25µA(sinking)
IOUT = 25µA(sourcing)
0.2
4.2
0.8
5.1
V
V
HIGH
3.8
Current Limit
Wake Up = 5V
Wake Up = 0V
0.025
.05
1.00
7.00
3.50
mA
mA
Package Lead Description
Package Lead #
Lead Symbol
Function
8 L PDIP
1
2
VIN
Supply voltage to the IC.
WDI
CMOS/TTL compatible input lead. The watchdog function monitors
the falling edge of the incoming signal.
3
4
Wake Up
RESET
CMOS/TTL compatible output consisting of a continuously generated
signal used to Wake Up the microprocessor from sleep mode.
CMOS/TTL compatible output lead RESET goes low whenever VOUT
drops by more than 6% from nominal, or during the absence of a cor-
rect watchdog signal.
5
7
8
Delay
Gnd
Input lead from timing capacitor for RESET and Wake Up signal.
Ground Connection
VOUT
Regulated output voltage 5V ± 2%.
3
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
