Application Notes
The duration of the reset pulse is given by:
TWDI(RESET)(typ) = (1 x 104) x CDELAY
Energy Conservation and Smart Features
Energy conservation is another benefit of using a regulator
with integrated microprocessor control features. Using the
CS8140 or CS8141 as indicated in Figure 8, the micropro-
cessor can control its own power down sequence. The
momentary contact switch quickly charges C1 through R1.
This has a tolerance of ±50% due to the IC, and ±10% due
to the capacitor.
The duration of the reset pulse ranges from 3.69ms to
13.5ms.
When the voltage across C1 reaches 3.95V ( the enable
threshold), the output switches on and VOUT rises to 5V.
After a delay period determined by CDelay, a frequency
programmable reset pulse train is generated at the reset
output. The pulse train continues until the correct watch-
dog signal appears at the WDI lead. C1 is now left to dis-
charge through the input impedance of the enable lead
(approximately 150k½) and the enable signal disappears.
The output voltage remains at 5V as long as the CS8140
continues to receive the correct watchdog signal.
The watchdog signal can be expressed as a frequency or
time. From a programmers point of view, time is more
useful since they must ensure that a watchdog signal is
issued consistently several times per second.
The maximum and minimum watchdog times are given
by:
tWDI(LOWER) = (1.3 x 105)CDELAY
tWDI(UPPER) = (3.82 x 104)CDELAY
There is a tolerance of ±20% due to the CS8140.
The microprocessor can power itself down by terminating
its watchdog signal. When the microprocessor finishes its
housekeeping or power down software routine, it stops
sending a watchdog signal. In response, the regulator
generates a reset signal and goes into a sleep mode where
VOUT drops to 0V, shutting down the microprocessor.
With a capacitor tolerance of ±10%:
tWDI(LOWER) = (1.3 x 105) x 1.20 x 1.1 x CDELAY
tWDI(UPPER) = (3.82 x 104) x 0.8 x 0.9 x CDELAY
tWDI(LOWER) = 141ms(max)
tWDI(UPPER) = 22.5ms (max)
Stability Considerations
The output or compensation capacitor C2 in Figure 7 helps
determine three main characteristics of a linear regulator:
start-up delay, load transient response and loop stability.
tWDI(LOWER) = (1.3 x 105) x 0.8 x 0.9 x CDELAY
tWDI(UPPER) = (3.82 x 104) x 1.2 x 1.1 x CDELAY
The capacitor value and type should be based on cost,
availability, size and temperature constraints. A tantalum
or aluminum electrolytic capacitor is best, since a film or
ceramic capacitor with almost zero ESR can cause instabili-
ty. The aluminum electrolytic capacitor is the least expen-
sive solution, but, if the circuit operates at low tempera-
tures (-25¡C to -40¡C), both the value and ESR of the
capacitor will vary considerably. The capacitor manufac-
turers data sheet usually provide this information.
tWDI(LOWER) = 76ms(min)
tWDI(UPPER) = 41ms (min)
The software must be written so that a watchdog signal
arrives at least every 76ms but not faster than every 41ms
(Figure 5).
PASS
FAIL
FAIL
The value for the output capacitor C2 in Figure 7 should
work for most applications, however it is not necessarily
the optimized solution.
7
9
24
41
32
31
44
13
76
Hz
ms
To determine an acceptable value for C2 for a particular
application, start with a tantalum capacitor of the recom-
mended value and work towards a less expensive alterna-
tive part.
141
107
22.5
C = 0.1mF ± 10%
Figure 5: WDI signal for CDelay = 0.82µF using CS8140.
Step 1: Place the completed circuit with a tantalum capac-
itor of the recommended value in an environmental cham-
ber at the lowest specified operating temperature and
monitor the outputs with an oscilloscope. A decade box
connected in series with the capacitor will simulate the
higher ESR of an aluminum capacitor. Leave the decade
box outside the chamber, the small resistance added by the
longer leads is negligible.
The CS8141 is identical to the CS8140 except that the
CS8141 only has a lower watchdog frequency threshold.
The designer using this part need only be concerned with
tWDI(LOWER) as shown in Figure 6.
FAIL
Step 2: With the input voltage at its maximum value,
increase the load current slowly from zero to full load
while observing the output for any oscillations. If no oscil-
lations are observed, the capacitor is large enough to
ensure a stable design under steady state conditions.
PASS
7
13
76
Hz
ms
141
Figure 6: WDI signal for CDelay = 0.82µF using CS8141.
9
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
