Circuit Description: continued
As long as ENABLE is high or ENABLE is low and the
RESET Circuit Waveforms with Delays Indicated
Watchdog signal is normal, VOUT will be at 5V (typ). If
ENABLE is low and the Watchdog signal moves outside
programmable limits, the output transistor turns off and
the IC goes into SLEEP mode. Only the ENABLE circuitry
in the IC remains powered up, drawing a quiescent cur-
rent of 250µA.
VOUT
VR
HI
VR
LO
RESET
The Watchdog monitors the frequency of an incoming
WDI signal. If the signal falls outside of the WDI window,
a frequency programmable pulse train is generated at the
VR
LO
VR
PEAK
lead (Figure 3) until the correct Watchdog input
RESET
tPOR
signal reappears at the lead (ENABLE = HIGH).
The lower and upper window threshold limits of the
watchdog function are set by the value of CDELAY. The lim-
its are determined according to the following equations for
the CS8140:
4a: Power RESET and Power Down
VOUT
tWDILOWER = (1.3 x 105)CDELAY or
VOUT -4.5%
(a)
³2ms
<2mS
fWDI(LOWER) = (7.69 x 10-6)CDELAY
-1
(b)
tWDI(UPPER) = (3.82 x 10-4)CDELAY or
fWDI(UPPER) = (2.62 x 10-5)CDELAY
-1
RESET
5V
For the CS8141 the lower limit is determined by the equa-
tions in (a) above.
tPOR
The capacitor CDELAY also determines the frequency of the
signal and the POWER-ON-
(POR) delay
RESET
period.
RESET
4b: Undervoltage Triggered RESET
If an undervoltage condition exists, the voltage on the
RESET
RESET
Function
lead goes low and the delay capacitor, CDELAY, is
discharged. remains low until output is in regula-
The
function is activated when the Watchdog sig-
RESET
RESET
nal is outside of its preset window (Figure 3), when the
regulator is in its power up state (Figure 4a) or when VOUT
drops below VOUT -4.5% for more than 2µs (Figure 4b.)
tion, the voltage on CDELAY exceeds the upper switching
threshold and the Watchdog input signal is within its set
window limits (Figure 4). The delay after the output is in
regulation is:
If the Watchdog signal falls outside of the preset voltage
and frequency window, a frequency programmable pulse
tPOR(typ) = (4.75 x 105) CDELAY
train is generated at the
lead (Figure 3) until the
RESET
correct Watchdog input signal reappears at the lead. The
duration of the pulse is determined by C
The
delay circuit is also programmed with the
RESET
external cap CDELAY
RESET
according to the following equation:
DELAY
.
The output of the reset circuit is an open collector NPN.
is operational down to V = 1V. Both and
RESET
RESET
tWDI(
) = (1 x104)CDELAY
OUT
RESET
its delay are governed by comparators with hysteresis to
avoid undesirable oscillations.
Application Notes
Assume that the reset delay must be 200ms minimum.
CS8140 Design Example
From the CS8140 data sheet the reset delay has a ±37% tol-
erance due to the regulator.
The CS8140 with its unique integration of linear regulator
and control features: , ENABLE and WATCHDOG,
RESET
Assume the capacitor tolerance is ±10%.
provides a single IC solution for a microprocessor power
supply. The reset delay, reset duration and watchdog fre-
quency limits are all determined by a single capacitor. For
a particular microprocessor the overriding requirement is
usually the reset delay (also known as power on reset).
The capacitor is chosen to meet this requirement and the
reset duration and watchdog frequency follow.
tPOR (min) = (4.75 x 105 x 0.63) x CDELAY x 0.9
tPOR (min)
CDELAY (min) =
2.69 x 105
CDELAY = (min) = 0.743 µF
Closest standard value is 0.82µF.
The reset delay is given by:
Minimum and maximum delays using 0.82µF are 220ms
and 586ms.
tPOR(typ) = (4.75 x 105)CDELAY
8
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
