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CS8129YTHA5 参数 Datasheet PDF下载

CS8129YTHA5图片预览
型号: CS8129YTHA5
PDF下载: 下载PDF文件 查看货源
内容描述: 5V , 750毫安低压差线性稳压器,具有低复位阈值 [5V, 750mA Low Dropout Linear Regulator with Lower RESET Threshold]
分类和应用: 线性稳压器IC调节器电源电路输出元件局域网
文件页数/大小: 8 页 / 191 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
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RESET  
Circuit Waveform  
(1) = No Delay Capacitor  
(2) = With Delay Capacitor  
V
OUT  
V
RH  
V
V
RT(ON)  
RESET  
(3) = Max:  
Voltage (1.0V)  
RT(OFF)  
(1)  
RESET  
(2)  
(3)  
V
RL  
t
Delay  
Delay  
V
DH  
V
DC(HI)  
V
DC(LO)  
V
DIS  
(2)  
RESET Circuit Functional Description  
put voltage is above VRT(ON). Otherwise, the Delay lead  
sinks current to ground (used to discharge the delay  
capacitor). The discharge current is latched ON when the  
output voltage is below VRT(OFF). The Delay capacitor is  
fully discharged anytime the output voltage falls out of  
regulation, even for a short period of time. This feature  
The CS8129  
function has hysteresis on both the  
RESET  
reset and delay comparators, a latching Delay capacitor  
discharge circuit, and operates down to 1V.  
The  
circuit output is an open collector type with  
RESET  
ON and OFF parameters as specified. The RESET output  
NPN transistor is controlled by the two circuits described  
(see Block Diagram).  
ensures a controlled  
pulse is generated following  
RESET  
detection of an error condition. The circuit allows  
the output transistor to go to the OFF (open) state  
RESET  
only when the voltage on the Delay lead is higher than  
VDC(HI)  
Low Voltage Inhibit Circuit  
.
This circuit monitors output voltage, and when output  
voltage is below the specified minimum causes the  
The Delay time for the  
the formula:  
function is calculated from  
RESET  
output transistor to be in the ON (saturation)  
RESET  
C
Delay x VDelay Threshold  
ICharge  
state. When the output voltage is above the specified level,  
this circuit permits the RESET output transistor to go into  
Delay time =  
the OFF state if allowed by the  
Delay circuit.  
RESET  
Delay time = CDelay(µF) x 3.2 x 105  
Reset Delay Circuit  
If CDelay=0.1µF, Delay time (ms)=32ms ± 50%: i.e. 16ms to  
48ms. The tolerance of the capacitor must be taken into  
account to calculate the total variation in the delay time.  
This circuit provides a programmable (by external capaci-  
tor) delay on the output lead. The Delay lead pro-  
vides source current to the external delay capacitor only  
when the "Low Voltage Inhibit" circuit indicates that out-  
RESET  
5