RESET Circuit Waveform
(1) = No Delay Capacitor
(2) = With Delay Capacitor
(3) = Max: RESET Voltage (1.0V)
VOUT
VRH
VRTH
VRTL
(1)
RESET
(2)
(3)
VRL
TD
Delay
VDH
VDTC
VDTD
VDIS
(2)
RESET Circuit Functional Description
The CS8128
on both the
function is very precise, has hysteresis
and Delay comparators, a latching
RESET
RESET
RESET Delay Circuit
This circuit provides a programmable (by external capaci-
Delay capacitor discharge circuit, and operation down to
1V.
tor) delay on the output lead. The Delay lead pro-
RESET
vides source current to the external delay capacitor only
when the Low Voltage Inhibit circuit indicates that output
voltage is above VRTH. Otherwise, the Delay lead sinks
current to ground (used to discharge the Delay capacitor).
The discharge current is latched ON when the output volt-
age falls below VRTL. The Delay capacitor is fully dis-
charged anytime the output voltage falls out of regulation,
even for a short period of time. This feature ensures a con-
The reset circuit output is an open collector type with ON
and OFF parameters as specified. The reset output NPN
transistor is controlled by the Low Voltage Inhibit and
Reset Delay circuits (see Block Diagram).
Low Voltage Inhibit Circuit
This circuit monitors output voltage, and when output
voltage is below VRTL, causes the reset output transistor to
be in the ON (saturation) state. When the output voltage is
above VRTH, this circuit permits the reset output transistor
to go into the OFF state if allowed by the reset Delay cir-
cuit.
trolled
pulse is generated following the detection
RESET
of an error condition. The circuit allows the
out-
RESET
put transistor to go to the OFF (open) state only when the
voltage on the Delay lead is higher than VDTC
.
4
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
