Circuit Description: continued
If the input voltage rises above 26V (e.g. load dump), the provide good noise immunity.
RESET
output shuts down. This response protects the internal cir-
cuitry and enables the IC to survive unexpected voltage
transients.
Function
signal (low voltage) is generated as the IC pow-
ers up (VOUT > VOUT - 100mV) or when VOUT drops out of
regulation (VOUT < VOUT - 140mV, typ). 40mV of hysteresis
is included in the function to minimize oscillations.
RESET
A
Using an emitter sense scheme, the amount of current
through the NPN pass transistor is monitored. Feedback
circuitry insures that the output current never exceeds a
preset limit.
RESET
The
output is an open collector NPN transistor,
controlled by a low voltage detection circuit. The circuit is
functionally independent of the rest of the IC, thereby
Should the junction temperature of the power device
exceed 180ûC (typ) the power transistor is turned off.
Thermal shutdown is an effective means to prevent die
overheating since the power transistor is the principle heat
source in the IC.
VOUT
5V to mP
and
System
Power
C
22mF
2
R
Regulator Control Functions
RST
CS–8120
The CS8120 contains two microprocessor compatible con-
to mP
RESET
Port
ENABLE
RESET
trol functions:
and
(Figure 3).
RESET
ENABLE
Function
C
RST
ENABLE
switches the output transistor. When the voltage
lead exceeds 2.9V typ, the output pass
ENABLE
on the
transistor turns off, leaving a high impedance facing the
load. The IC will remain in Sleep mode, drawing only
250µA, until the voltage on the lead drops below 2.1V typ.
RESET
Figure 4: RC Network for
Delay circuitry
ENABLE
Hysteresis (800mV) is built into the
function to
RESET
guaranteeing that the
as 1V.
signal is valid for VOUT as low
RESET
FOR 7V < V < 26V
IN
An external RC network on the
lead (Figure 4) pro-
vides a sufficiently long delay for most microprocessor
based applications. RC values can be chosen using the fol-
lowing formula:
V
IN
R
TOT ´ CRST
ÐtDelay
ENABLE
HI
VIN(HI)
VT Ð VOUT
VRST Ð VOUT
[
]
LO
ln
)
(
VRT(ON)
VRT(OFF)
where:
V
OUT
RTOT = RRST in parallel with RIN,
RIN = µP port impedance,
(1)
VR
H
VR
PEAK
PEAK
CRST
tDelay = desired delay time,
RESET
RESET
= delay capacitor,
(2)
VR
SAT
RESET
(1) = NO RESET DELAY CAPACITOR
(2) = WITH RESET DELAY CAPACITOR
VRST = VSAT of
(0.7V @ turn - on), and
VT = µP logic threshold voltage.
lead
Figure 3: Circuit Waveforms for CS8120
Applications Notes
The circuit depicted in Figure 5 lets the microprocessor
control its power source, the CS8120 regulator. An I/O
port on the µP and the SWITCH port are used to drive the
base of Q1. When Q1 is driven into saturation, the voltage
by withdrawing drive current, once the SWITCH is open.
This software control at the I/O port allows the µP to fin-
ish key housekeeping functions before power is removed.
The logic options are summarized in Table 1 below
ENABLE
on the
regulatorÕs output is switched out. When the drive cur-
ENABLE
lead falls below its lower threshold. The
Table 1: Logic Control of CS8120 Output
rent is removed, the voltage on the
lead rises,
ENABLE
LOW
µP I/O drive
ON
SWITCH
Closed
Open
Output
ON
the output is switched off and the IC moves into Sleep
mode where it draws 250µA.
LOW
ON
ENABLE
By coupling these two controls with
, the system
has added flexibility. Once the system is running, the
state of the SWITCH is irrelevant as long as the I/O port
continues to drive Q1. The µP can turn off its own power
OFF
Closed
Open
LOW
ON
HIGH
OFF
5
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
