Application Information: continued
in the supply voltage. The duty cycle is varied based upon
the input voltage and supply voltage by the following
equation:
tial voltage across these two leads is amplified internally
and compared to the voltage at the IADJ lead. The gain, AV,
is set internally and externally by the following equation:
2.8 ´ VCTL
VI(ADJ)
37000
Duty Cycle = 100% ´
AV =
=
ISENSE+ - ISENSE-
1000 + RCS
VCC
The current limit (ILIM) is set by the external current sense
resistor (RSENSE) placed across the ISENSE+ and ISENSE- ter-
minals and the voltage at the IADJ lead.
An internal DC voltage equal to:
VDC = (1.683 ´ VCTL) + (VVALLEY
)
is compared to the oscillator voltage to produce the com-
pensated duty cycle. The transfer is set up so that at VCC
14V the duty will equal VCTL divided by VREG. For exam-
ple at VCC = 14V, VREG = 5V and VCTL = 2.5V, the duty
(1000 + RCS
37000
)
VI(ADJ)
RSENSE
=
ILIM
=
´
cycle would be 50% at the output. This would place a 7V
average voltage across the load. If VCC then drops to 10V,
the IC would change the duty cycle to 70% and hence keep
the average load voltage at 7V.
The RCS resistors and CCS components form a differential
low pass filter which filters out high frequency noise gen-
erated by the switching of the external MOSFET and the
associated lead noise. RCS also forms an error term in the
gain of the ILIM equation because the ISENSE+ and ISENSE-
120%
leads are low impedance inputs thereby creating a good
current sensing amplifier. Both leads source 50µA while
the chip is in run mode. RCS should be much less than 1000
½ to minimize error in the ILIM equation. IADJ should be
biased between 1V and 4V.
V
= 8V
CC
100%
80%
V
V
= 14V
= 16V
CC
CC
When the current through the external MOSFET exceeds
60%
40%
20%
0%
I
LIM, an internal latch is set and the output pulls the gate of
the MOSFET low for the remainder of the oscillator cycle
(fault mode). At the start of the next cycle, the latch is reset
and the IC reverts back to run mode until another fault
occurs. If a number of faults occur in a given period of
time, the IC Òtimes outÓ and disables the MOSFET for a
long period of time to let it cool off. This is accomplished
by charging the CFLT capacitor each time an over current
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
CTL Voltage (% of V
)
REG
condition occurs. If a cycle goes by with no overcurrent
fault occurring, an even smaller amount of charge will be
removed from CFLT. If enough faults occur together, even-
Figure 1: Voltage Compensation
tually CFLT will charge up to 2.4V and the fault latch will
be set. The fault latch will not be reset until the CFLT dis-
charges to 0.6V. This action will continue indefinitely if the
fault persists.
5V Linear Regulator
There is a 5V, 5mA linear regulator available at the VREG
lead for external use. This voltage acts as a reference for
many internal and external functions. It has a drop out of
approximately 1.5V at room temperature and does not
require an external capacitor for stability.
The off time and on time are set by the following:
2.4V - 0.6V
Off Time = CFLT
´
4.5µA
Current Sense and Timer
The IC differentially monitors the load current on a cycle
by cycle basis at the ISENSE+ and ISENSE- leads. The differen-
4
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
