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CS5661 参数 Datasheet PDF下载

CS5661图片预览
型号: CS5661
PDF下载: 下载PDF文件 查看货源
内容描述: 高性能双通道电流模式控制器, ENABLE [High Performance Dual Channel Current Mode Controller with ENABLE]
分类和应用: 控制器
文件页数/大小: 8 页 / 169 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
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Operating Description: continued  
outputs are disabled when the error amplifier output is at  
comparator has built-in hysteresis to prevent erratic output  
behavior as their respective thresholds are crossed. The  
its lowest state (VOUT(LOW)). This occurs when the power  
supply is operating at light or no-load conditions, or at the  
beginning of a soft-start interval.  
VCC comparator upper and lower thresholds are 8.4V and  
7.8V, respectively. The VREF comparator disables the out-  
puts until the internal circuitry is functional. This compara-  
tor has upper and lower thresholds of 3.6V and 3.4V. The  
guaranteed minimum operating voltage after turn-on is  
8.8V.  
The minimum allowable error amplifier feedback resis-  
tance is limited by the amplifier’s source current capability  
(0.5 mA) and the output voltage (VOUT(High)) required to  
reach the current sense comparator 1.0V clamp level with  
the error amplifier inverting input at ground. This condi-  
tion happens during initial system start up or when the  
sensed output is shorted:  
Outputs and Power Ground  
Each channel contains a single totem-pole output stage  
specifically designed for driving a power MOSFET. The  
outputs have up to ±400mA peak current capability and  
have a typical rise and fall time of 28ns with a 1.0nF load.  
Internal circuitry has been added to keep the outputs in  
active pull-down mode whenever undervoltage lockout is  
active. An external pull-down resistor is not needed.  
(3 x 1.0V) + 1.4V  
= 8.8kΩ  
RF(min)  
0.5mA  
Current Sense Comparator and PWM Latch  
Cross-conduction current in the totem-pole output stage  
has been minimized for high speed operation. The average  
added power due to cross-conduction with VCC=15V is  
only 60mW at 500kHz.  
The CS5661 operates as current mode controller. Output  
switch conduction is initiated by the oscillator and termi-  
nated when the peak inductor current reaches the thresh-  
old level established by the error amplifier output. The  
error signal controls the peak inductor current on a cycle-  
by-cycle basis. The current sense comparator-PWM latch  
combination ensures that only a single pulse appears at the  
output during any given oscillator cycle. The current is  
converted to a voltage by connecting sense resistor RSENSE  
in series with the source of output switch Q1 and ground.  
This voltage is monitored via the SENSE1,2 pins and com-  
pared to a voltage derived from the error amp output. The  
peak current under normal operating conditions is con-  
trolled by the voltage at COMP where:  
Although the outputs were optimized for MOSFET’s, they  
can easily supply the negative base current required by  
bipolar NPN transistors for enhanced turn-off. Because the  
outputs do not contain internal current limiting circuitry,  
an external series resistor may be required to prevent the  
peak output current from exceeding the ±400mA maxi-  
mum rating. The sink saturation voltage (VOL) is less than  
0.4V at 20mA.  
A separate Power Ground pin is provided and will signifi-  
cantly reduce the level of switching transient noise  
imposed on the control circuitry.  
VCOMP – 1.4V  
ENABLE2  
Ipk  
=
3RSENSE  
This input is used to switch VOUT . VOUT1 can be used to  
2
control circuitry that runs continuously; e.g. volatile mem-  
ory, the system clock, or a remote controlled receiver. The  
VOUT2 output can control the high power circuitry that can  
be turned off when not needed.  
Abnormal operating conditions occur when the power  
supply output is overloaded or if output voltage is too  
high. Under these conditions, the current sense comparator  
threshold will be internally clamped to 1.0V. Therefore the  
maximum peak switch current is:  
Voltage Reference  
1.0V  
RSENSE  
Ipk(max)  
=
The 5.0V bandgap reference is trimmed to ±2.0% tolerance.  
The reference has short circuit protection and is capable of  
sourcing 30mA for powering any additional external cir-  
cuitry.  
Erratic operation due to noise pickup can result if there is  
an excessive reduction of the Ipk(max) clamp voltage.  
Design Considerations  
A narrow spike on the leading edge of the current wave-  
form can usually be observed and may cause the power  
supply to exhibit an instability when the output is lightly  
loaded. The addition of an RC filter on the current sense  
input reduces this spike to an acceptable level.  
High frequency circuit layout techniques are imperative to  
prevent pulse-width jitter. This is usually caused by exces-  
sive noise pick-up imposed on the current sense or voltage  
feed-back inputs. Noise immunity can be improved by  
lowering circuit impedances at these points. The printed  
circuit board layout should contain a ground plane with  
low current signal and high current switch and output  
grounds returning on separate paths back to the input fil-  
Undervoltage Lockout  
Two undervoltage lockout comparators have been incor-  
porated to guarantee that the IC is fully functional before  
the output stages are enabled. VCC and the reference out-  
put VREF are monitored by separate comparators. Each  
6