Operating Description: continued
ter capacitor. Ceramic bypass capacitors (0.1µF) connected
error amp compensation circuitry and the converter out-
put voltage-divider should be located close to the IC and
as far as possible from the power switch and other noise
generating components.
directly to VCC and VREF may be required to improve noise
filtering. This provides a low impedance path for filtering
the high frequency noise. All high current loops should be
kept as short as possible using heavy copper runs. The
Timing Diagram
SYNC
Capacitor C
T
Latch 1
“Set” Input
COMP
Sense
1
1
Latch 1
“Reset” Input
V
OUT
1
ENABLE
2
0V
Latch 2
“Set” Input
COMP
Sense
2
2
Latch 2
“Reset” Input
V
OUT
2
Typical Application Diagram
V
IN
Dual Boost Regulator
V
CC
C
+
F1
5.0V
Reference
+
-
Regulator
C
V
F2
Internal
REF
R
R
+
-
Bias
+
V
CC
UVLO
2.5V
14V
-
+
V
REF
UVLO
3.4V
L
1
-
D
1
20kΩ
V
OUT
1
Sync
+
+
C
C
OUT
1
L
2
Q1
Oscillator
V
R
OUT
+
R
1
T
C
T
PWM
V
OUT
1
Latch 1
Current Sense
Comparator 1
R
FB
1
2R
S
Q
R
D
+
2
+
R
-
Sense
1
V
-
OUT
1.0V
2
REF
+
V
Error
Amp 1
FB
1
R
FB
2
1.0V
OUT
2
COMP
1
Sense
V
1
250µA
ENABLE
Q2
2
+
PWM
V
OUT
OUT
2
Current Sense
Comparator 2
2
Latch 2
S
R
R
R
2R
FB
Q
3
+
+
-
-
1.0mA
V
Error
Amp 2
FB
R
2
1.0V
R
FB
4
Sense
COMP
2
2
R
Sense
2
Gnd
Pwr Gnd
7
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
