CS5302
ELECTRICAL CHARACTERISTICS (continued) (0°C < T < 70°C; 0°C < T < 125°C; 4.7 V < V
< 14 V; 10 V < V
< 20 V;
CCH
A
J
CCL
C
= 3.3 nF, C
= 3.3 nF, R
= 32.4 k, C
= 1.0 nF, C = 0.1 µF, C
= 0.1 µF, DAC Code 1001, C = 1.0 µF,
VCC
GATE(H)
GATE(L)
R(OSC)
COMP
SS
REF
I
≥ 1.0 V; unless otherwise specified.)
LIM
Characteristic
Test Conditions
Min
Typ
Max
Unit
PWM Comparators
Minimum Pulse Width
Measured from CSx to GATE(H)
V(V ) = V(CS ) = 1.0 V, V(COMP) = 1.5 V
–
350
515
0.5
ns
V
FB
REF
60 mV step applied between V
and V
CREF
CSX
Channel Start Up Offset
0.3
0.4
V(CS1) = V(CS2) = V(V ) = V(CS
) = 0 V;
REF
FB
Measure V(COMP) when GATE(H)1, (H)2,
switch high
Gate(H) and Gate(L)
High Voltage (AC)
Note 1. Measure V
– Gate(L) or
–
0
1.0
V
CCLX
X
V
CCHX
– Gate(H)
X
Low Voltage (AC)
Note 1. Measure Gate(L) or Gate(H)
–
–
0
0.5
80
V
X
X
Rise Time Gate(H)
1.0 V < GATE < 8.0 V; V
1.0 V < GATE < 8.0 V; V
8.0 V > GATE > 1.0 V; V
8.0 V > GATE > 1.0 V; V
= 10 V
= 10 V
= 10 V
= 10 V
35
35
35
35
65
65
1.2
ns
ns
ns
ns
ns
ns
V
X
CCHX
CCLX
CCHX
CCLX
Rise Time Gate(L)
–
80
X
Fall Time Gate(H)
–
80
X
Fall Time Gate(L)
–
80
X
Gate(H) to Gate(L) Delay
Gate(L) to Gate(H) Delay
GATE Pull–down
Gate(H) < 2.0 V, Gate(L) > 2.0 V
30
30
–
110
110
1.6
X
X
Gate(L) < 2.0 V, Gate(H) > 2.0 V
X
X
Force 100 µA into Gate Driver with no power
applied to V and V = 2 V.
CCHX
CCLX
Oscillator
Switching Frequency
Switching Frequency
Switching Frequency
Measure any phase (R
= 32.4 k)
300
150
600
–
400
200
800
1.0
500
250
1000
–
kHz
kHz
kHz
V
OSC
Note 1. Measure any phase (R
= 63.4 k)
= 16.2 k)
OSC
OSC
Note 1. Measure any phase (R
R
Voltage
–
–
OSC
Phase Delay
165
180
195
deg
Adaptive Voltage Positioning
V
Output Voltage to DAC
Offset
CS1 = CS2 = CS , V = COMP
REF FB
–15
240
2.4
–
15
380
3.8
mV
mV
V/V
DRP
OUT
Measure V
– COMP
DRP
Maximum V
Voltage
(CS1 = CS2) – C
= 50 mV,
310
3.0
DRP
REF
V
FB
= COMP, Measure V
– COMP
DRP
Current Sense Amp to V
Gain
–
DRP
Current Sensing and Sharing
CS Input Bias Current
V(CSx) = V(CS
V(CSx) = V(CS
) = 0 V
–
0.5
4.0
µA
REF
REF
CS1–CS2 Input Bias Current
Current Sense Amplifiers Gain
) = 0 V
–
–
0.2
2.0
µA
REF
2.8
3.15
3.53
V/V
Current Sense Amp Mismatch
Note 1. 0 ≤ (CSx – CS
) ≤ 50 mV
REF
–5.0
0
–
–
5.0
mV
V
Current Sense Amplifiers Input
Common Mode Range Limit
Note 1.
V
– 2
CCL
Current Sense Input to I
Gain
0.25 V < I
< 1.20 V
LIM
5.0
4.0
6.25
10
8.0
26
V/V
LIM
Current Limit Filter Slew Rate
Note 1.
mV/µs
1. Guaranteed by design. Not tested in production.
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