Circuit Description
When the power supply sees a sudden large output cur-
Setting the Oscillator
rent increase, the control voltage will increase allowing the
duty cycle to momentarily increase. Since the duty cycle
tends to exceed the maximum allowed to prevent trans-
former saturation in some power supplies, the internal
oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of oscillator timing
components.
The times Tc and Td can be determined as follows:
VREF - VLOWER
tc = RTCT ln
(
)
VREF - VUPPER
VREF - IdRT - VLOWER
VREF - IdRT - VUPPER
td = RTCT ln
(
)
V
OSC
OSC
RESET
Substituting in typical values for the parameters in the
above formulas:
Toggle
F/F Output
VREF = 5.0V, VUPPER = 2.7V, VLOWER = 1.0V, Id = 8.3mA,
then
EA Output
Switch
Current
tc ≈ 0.5534RTCT
V
CC
I
O
O
2.3 - 0.0083 RT
td = RTCT ln
(
)
4.0 - 0.0083 RT
V
For better accuracy R should be ≥10kΩ.
T
Figure 2: Timing Diagram
Grounding
High peak currents associated with capacitive loads neces-
sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Gnd in a single
point ground.
VREF
OSC
Gnd
RT
CT
The transistor and 5kΩ potentiometer are used to sample
the oscillator waveform and apply an adjustable ramp to
Sense.
Vupper
Vlower
tc
td
Sawtooth Mode
LARGE RT (≈10kΩ)
VOSC
Internal Clock
Triangular Mode
SMALL RT (≈700kΩ)
VREF
Internal Clock
Figure 3: Oscillator Timing Network and Parameters
5
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
