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CS5166HGDW16 参数 Datasheet PDF下载

CS5166HGDW16图片预览
型号: CS5166HGDW16
PDF下载: 下载PDF文件 查看货源
内容描述: 5位同步CPU控制器与电源就绪和电流限制 [5-Bit Synchronous CPU Controller with Power-Good and Current Limit]
分类和应用: 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件页数/大小: 22 页 / 441 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
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Application Information  
of the CS5166H single pole feedback loop and demon-  
Theory Of Operation  
V2TM Control Method  
strates the overall stability of the CS5166H-based regulator.  
The V2TM method of control uses a ramp signal that is gen-  
erated by the ESR of the output capacitors. This ramp is  
proportional to the AC current through the main inductor  
and is offset by the value of the DC output voltage. This  
control scheme inherently compensates for variation in  
either line or load conditions, since the ramp signal is gen-  
erated from the output voltage itself. This control scheme  
differs from traditional techniques such as voltage mode,  
which generates an artificial ramp, and current mode,  
which generates a ramp from inductor current.  
.1µF  
10K  
Open Loop  
49.63  
PWM  
Comparator  
BW  
+
62.3 KHz  
GATE(H)  
C
Phase margin  
81.9  
GATE(L)  
Figure 2: Feedback loop Bode Plot.  
Ramp Signal  
V
FB  
Line and load regulation are drastically improved because  
there are two independent voltage loops. A voltage mode  
controller relies on a change in the error signal to compen-  
sate for a deviation in either line or load voltage. This  
change in the error signal causes the output voltage to  
change corresponding to the gain of the error amplifier,  
which is normally specified as line and load regulation.  
A current mode controller maintains fixed error signal  
under deviation in the line voltage, since the slope of the  
ramp signal changes, but still relies on a change in the error  
signal for a deviation in load. The V2TM method of control  
maintains a fixed error signal for both line and load varia-  
tion, since the ramp signal is affected by both line and load.  
Error  
Amplifier  
+
COMP  
E
Reference  
Voltage  
Error  
Signal  
TM  
Figure 1: V2 Control Diagram.  
The V2TM control method is illustrated in Figure 1. The out-  
put voltage is used to generate both the error signal and  
the ramp signal. Since the ramp signal is simply the output  
voltage, it is affected by any change in the output regard-  
less of the origin of that change. The ramp signal also con-  
tains the DC portion of the output voltage, which allows  
the control circuit to drive the main switch to 0% or 100%  
duty cycle as required.  
Constant Off-Time  
To maximize transient response, the CS5166H uses a  
Constant Off-Time method to control the rate of output  
pulses. During normal operation, the Off-Time of the high  
side switch is terminated after a fixed period, set by the  
COFF capacitor. To maintain regulation, the V2TM Control  
Loop varies switch On-Time. The PWM comparator moni-  
tors the output voltage ramp, and terminates the switch  
On-Time.  
A change in line voltage changes the current ramp in the  
TM  
inductor, affecting the ramp signal, which causes the V2  
control scheme to compensate the duty cycle. Since the  
change in inductor current modifies the ramp signal, as in  
current mode control, the V2TM control scheme has the same  
advantages in line transient response.  
A change in load current will have an affect on the output  
voltage, altering the ramp signal. A load step immediately  
changes the state of the comparator output, which controls  
the main switch. Load transient response is determined  
only by the comparator response time and the transition  
speed of the main switch. The reaction time to an output  
load step has no relation to the crossover frequency of the  
error signal loop, as in traditional control methods.  
Constant Off-Time provides a number of advantages.  
Switch duty Cycle can be adjusted from 0 to 100% on a  
pulse-by pulse basis when responding to transient condi-  
tions. Both 0% and 100% Duty Cycle operation can be  
maintained for extended periods of time in response to  
Load or Line transients. PWM Slope Compensation to  
avoid sub-harmonic oscillations at high duty cycles is  
avoided.  
The error signal loop can have a low crossover frequency,  
since transient response is handled by the ramp signal  
loop. The main purpose of this ‘slow’ feedback loop is to  
provide DC accuracy. Noise immunity is significantly  
improved, since the error amplifier bandwidth can be  
rolled off at a low frequency. Enhanced noise immunity  
improves remote sensing of the output voltage, since the  
noise associated with long feedback traces can be effective-  
ly filtered.  
Switch On-Time is limited by an internal 30µs (typical)  
timer, minimizing stress to the Power Components  
Programmable Output  
The CS-5166H is designed to provide two methods for pro-  
gramming the output voltage of the power supply. A five  
bit on board digital to analog converter (DAC) is used to  
program the output voltage within two different ranges.  
The Bode plot in Figure 2 shows the gain and phase margin  
7