Electrical Characteristics: 0˚C < TA < 70˚C; 0˚C < TJ < 125˚C; 8V < VCC < 14V; 2.0V DAC Code
(VID4 = VID3 = VID2 = VID1 =0, VID0 = 1), CGATE(H) = CGATE(L) = 3.3nF, COFF = 330pF, CSS= 0.1µF; Unless otherwise stated.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
ꢀꢀVCC Supply Current
Operating
1V<VFB<VDAC (Max On-Time),
No Loads on GATE(H) and GATE(L)
12
20
mA
ꢀ VCC Monitor
Start Threshold
Stop Threshold
Hysteresis
GATE(H) Switching
GATE(H) not switching
Start – Stop
3.75
3.65
3.95
3.87
80
4.15
4.05
V
V
mV
ꢀ Error Amplifier
V
FB Bias Current
VFB = 0V
0.1
30
1.0
1.0
60
1.15
µA
µA
V
COMP Source Current
COMP CLAMP Voltage
COMP = 1.2V to 3.6V; VFB = 1.9V
VFB = 1.9V, Adjust COMP voltage
for Comp current = 60µA
COMP = 0V
15
0.85
COMP Clamp Current
COMP Sink Current
Open Loop Gain
Unity Gain Bandwidth
PSRR @ 1kHZ
0.4
180
50
0.5
60
1.0
400
60
2
1.6
800
mA
µA
dB
MHz
dB
V
COMP=1.2V; VFB=2.2V; VSS > 2.5V
Note 1
Note 1
Note 1
85
ꢀ GATE(H) and GATE(L)
High Voltage at 100mA
Low Voltage at 100mA
Rise Time
Measure VCC –GATE
Measure GATE
1.6V < GATE < (VCC – 2.5V)
(VCC – 2.5V) >GATE > 1.6V
GATE(H)<2V, GATE(L)>2V
GATE(L)<2V, GATE(H)>2V
Resistance to PGnd (Note 1)
1.2
1.0
40
40
65
65
50
2.0
1.5
80
V
V
ns
ns
ns
ns
kΩ
Fall Time
80
GATE(H) to GATE(L) Delay
GATE(L) to GATE(H) Delay
GATE pull-down
30
30
20
100
100
115
ꢀ Over Current Detection
Current limit voltage
V
FB = 0V to 3.5V
55
13
76
30
130
50
mV
µA
8V < VCC < 12V + 10%
ISENSE = 2.8V
ISENSE Bias Current
ꢀ Fault Protection
SS Charge Time
SS Pulse Period
SS Duty Cycle
V
V
FB = 3V, VISENSE = 2.8V
FB = 3V, VISENSE = 2.8V
1.6
25
1.0
3.3
100
3.3
5.0
200
6.0
ms
ms
%
(Charge Time/Period) × 100
3
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
