Application Information
As shown in Figure 5, the BOOST pin current includes a
VC × CCOMP
ISOURCE
TSS
=
constant 7mA pre-driver current and base current propor-
tional to switch conducting current. A detailed discussion
of this current is conducted in Thermal Consideration sec-
tion. A 0.1µF capacitor is usually adequate for maintaining
the Boost pin voltage during the on time.
where VC = VC pin steady-state voltage, which is approxi-
mately equal to error amplifier’s reference
voltage.
CCOMP = Compensation capacitor connected to the
VC pin
30
25
ISOURCE = OUTPUT SOURCE CURRENT of the
error amplifier.
Using a 0.1µF Ccomp, the calculation shows a TSS over 5ms
which is adequate to avoid any current stresses. Figure 6
shows the gradual rise of the VC, VO and envelope of the
20
15
10
5
V
SW during power up. There is no voltage over-shoot after
the output voltage reaches the regulation. If the supply
voltage rises slower than the VC pin, output voltage may
over-shoot.
0
1
1.5
0.5
0
Switching Current (A)
Figure 5: The boost pin current includes 7mA pre-driver current and
base current when the switch is turned on. The beta decline of the
power switch further increases the base current at high switching cur-
rent.
BIAS Pin (CS51412 and CS51414 Only)
The BIAS pin allows a secondary power supply to bias the
control circuitry of the IC. The BIAS pin voltage should be
between 3.3V and 6.0V. If the BIAS pin voltage falls below
that range, use a diode to prevent current drain from the
BIAS pin. Powering the IC with a voltage lower than the
regulator’s input voltage reduces the IC power dissipation
and improves energy transfer efficiency.
Figure 6: The power up transition of C5141X regulator.
Short Circuit
Shutdown
When the VFB pin voltage drops below FOLDBACK
THRESHOLD, the regulator reduces the peak current limit
by 40% and switching frequency to 1/ 4 of the nominal fre-
quency. These features are designed to protect the IC and
external components during over load or short circuit con-
ditions. In those conditions, peak switching current is
clamped to the current limit threshold. The reduced
switching frequency significantly increases the ripple cur-
rent, and thus lowers the DC current. The short circuit can
causes the minimum duty cycle to be limited by MINI-
MUM OUTPUT PULSE WIDTH. The foldback frequency
reduces the minimum duty cycle by extending the switch-
ing cycle. This protects the IC from overheating, and also
limits the power that can be transferred to the output. The
current limit foldback effectively reduces the current stress
on the inductor and diode. When the output is shorted, the
DC current of the inductor and diode can approach the
current limit threshold. Therefore, reducing the current
limit by 40% can result in an equal percentage drop of the
inductor and diode current. The short circuit waveforms
are captured in Figure 7, and the benefit of the foldback
frequency and current limit is self-evident.
The internal power switch will not turn on until the VIN pin
rises above the START UP VOLTAGE. This ensures no
switching until adequate supply voltage is provided to the
IC.
The IC enters a sleep mode when the SHDNB pin is pulled
below SHUTDOWN THRESHOLD VOLTAGE. In the sleep
mode, the power switch keeps open and the supply current
reduces to SHUTDOWN QUIESCENT CURRENT. This pin
has internal pull-up current. So when this pin is not used,
leave the SHDNB pin open.
Start-Up
During power up, the regulator tends to quickly charge up
the output capacitors to reach voltage regulation. This
gives rise to an excessive in-rush current which can be
TM
detrimental to the inductor, IC and catch diode. In V2
control , the compensation capacitor provides soft-start
with no need for extra pin or circuitry. During the power
up, the OUTPUT SOURCE CURRENT of the error amplifi-
er charges the compensation capacitor which forces VC pin
and thus output voltage ramp up gradually. The soft-start
duration can be calculated by
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CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
