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CS51311GDR14 参数 Datasheet PDF下载

CS51311GDR14图片预览
型号: CS51311GDR14
PDF下载: 下载PDF文件 查看货源
内容描述: CPU同步降压控制器的12V和5V的应用 [Synchronous CPU Buck Controller for 12V and 5V Applications]
分类和应用: 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件页数/大小: 19 页 / 239 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
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Application Information: continued  
regulator output exceeds the voltage on the COMP pin  
plus the 1.1V PWM comparator offset prior to the drop  
across the current sense resistor exceeding the current limit  
threshold. In this case, the PWM control loop has achieved  
regulation and the initial pulse is then followed by a con-  
stant off time as programmed by the COFF capacitor. The  
COMP capacitor will continue to slowly charge and the  
regulator output voltage will follow it, less the 1.1V PWM  
offset, until it achieves the voltage programmed by the  
DAC’s VID input. The Error Amp will then source or sink  
current to the COMP cap as required to maintain the cor-  
rect regulator DC output voltage. Since the rate of increase  
of the COMP pin voltage is typically set much slower than  
the regulator’s slew capability, inrush current, output volt-  
age, and duty cycle all gradually increase from zero. (See  
Figures 7, 8, and 9).  
Duty Cycle = VOUT / VIN  
0.27V / 3.54V = 7% 5.2%  
Figure 9: Pulse-by-Pulse Regulation during Soft Start (2µs/div).  
Channel 1 - Regulator Output Voltage (1V/div)  
Channel 2 – Inductor Switching Node (5V/div)  
Channel 3 - VCC (10V/div)  
Start-up @  
VCC > 8.4V  
Channel 4 - Regulator Input Voltage (5V/div)  
If the voltage across the Current Sense resistor generates a  
voltage difference between the VFB and VOUT pins that  
exceeds the OVC Comparator Offset Voltage (86mV typi-  
cal), the Fault latch is set. This causes the COMP pin to be  
quickly discharged, turning off GATE(H) and the upper  
NFET since the voltage on the COMP pin is now less than  
the 1.1V PWM comparator offset. The Fault latch is reset  
when the voltage on the COMP decreases below the  
Discharge threshold voltage (0.25V typical). The COMP  
capacitor will again begin to charge, and when it exceeds  
the 1.1V PWM comparator offset, the regulator output will  
Soft Start normally (see Figure 10).  
Figure 7: Normal Startup (2ms/div).  
Channel 1 - Regulator Output Voltage (1V/div)  
Channel 2 - COMP Pin (1V/div)  
Because the start-up circuit depends on the current sense  
function, a current sense resistor should always be used.  
Channel 3 - VCC (10V/div)  
Channel 4 - Regulator Input Voltage (5V/div)  
OCP @  
VCC > 8.4V  
Start-up @  
VCC > 8.4V  
Initial Pulse until VOUT  
> COMP + PWM Offset  
Soft Start @  
COMP > 1.1V  
Figure 8: Normal Startup showing initial pulse followed by Soft Start  
(20µs/div).  
Channel 1 - Regulator Output Voltage (1V/div)  
Channel 2 – Inductor Switching Node (5V/div)  
Channel 3 - VCC (10V/div)  
Figure 10: Startup with COMP pre-charged to 2V (2ms/div).  
Channel 1 - Regulator Output Voltage (1V/div)  
Channel 2 - COMP Pin (1V/div)  
Channel 3 - VCC (10V/div)  
Channel 4 - Regulator Input Voltage (5V/div)  
Channel 4 - Regulator Input Voltage (5V/div)  
8