Application Notes: continued
V
IN
Pole due to error amplifier
output impedance and C
1
A
f
z
= 1/2πR C
4 1
V
V
OUT
V
OUT
= 18V, Select > 2V
= 16V, Select < 0.8V
ENABLE
IN
f
P
= 1/πR C
4 2
NC
NC
V
REG
+G
C
L=33µH
5V
G
V
LIN
B
100µF
ESR<8Ω
error amplifier gain
-20dB/dec
V
I
SW
BIAS
C
OUT
R
BIAS
= 64.9kΩ
(2)
Gnd
Gnd
Gnd
88µF
Gnd
f
P
= 1/π R
C
Load OUT
R
1
100kΩ
Gnd
Gnd
Gnd
Gnd
f
CO
MICROPROCESSOR
0
V
V
RESET
FB1
R
(1)
946Ω
7.5kΩ
2
C
Delay
FB2
C
0.1µF
modulator gain + feedback resistor divider attenuation
delay
R
3
SELECT
COMP
WDI
-G
C
OSC
C
COMP
0.33µF
C
OSC
390pF
f
z
= 1/2π ESR C
OUT
Figure 10. Bode plot of error amplifier (OTA) gain and modulator gain
added to the feedback resistor divider attenuation.
Figure 11. A typical application diagram with external components con-
figured in a boost topology.
A pole at point C:
Step 9
fp = 1/(πR4C2),
(8g)
Finally the watchdog timer period and Power on Reset
time is determined by:
offsets the zero set by the ESR of the output capacitors.
An alternative scheme uses a single capacitor as shown in
Figure 11, to roll the gain off at a relatively low frequency.
tDelay = 1.353 × CDelayRBIAS
.
(9)
Linear Regulator Output Current vs. Input Voltage
100
100
75
50
25
0
75
50
25
0
Θ
= 35°C/W
JA
Θ
= 55°C/W
JA
V
IN
= 14V
V
IN
= 14V
Max Total Power = 1.86W
Max Total Power = 1.18W
15
30
15
30
0
5
10
20
25
0
5
10
20
25
V
REG
(V)
V
(V)
REG
Figure 12: The shaded area shows the safe operating area of the CS5111 as a function of ILIN, VREG, and ΘJA. Refer to the table below for typical
loads and voltages.
Worst Case Switcher
Power Available
(ΘJA = 55°C/W)
Worst Case Switcher
Power Available
(ΘJA = 35°C/W)
Linear Power
Dissipation
VREG
(V)
20
20
20
20
25
25
25
25
VIN
(V)
14
14
14
14
14
14
14
14
ILIN
(mA)
25
50
75
100
25
50
75
100
(W)
(W)
0.74
0.35
*
(W)
1.42
1.03
0.64
0.26
1.26
0.75
0.24
*
0.44
0.83
1.22
1.60
0.60
1.11
1.62
2.14
*
0.58
0.07
*
*
* Subjecting the CS5111 to these conditions will exceed the maximum total power that the part can handle, thereby forcing it into thermal limit.
9