Block Diagram
V
OUVDELAY
CC
Aux. Error Amp
1.2V
+
PROGRAM
5V
+
C1
G1
A1
OAOUT
OAM
-
V
RSFF
+
1.4V
-
R F1Q
-
G3
V
-
V
REFOK
Fault Latch
G18
V
S
C2
+
V
SS
C3
+
Output
Undervoltage
Timer
D1
Set Dominant
45k
ENABLE
UVSD
+
ENABLE
Comparator
RSFF
5k
Q
R
RUN 1
G4
C4
C7
-
-
F2
P1
S
V
Restart
C5
SS
G5
+
Comparator
Under Voltage
Comparator
1.4V
-
Reset
Dominant
+
5V
T
V
A2
PERIOD
V
+
-
100k
RUN1
Over Voltage
Comparator
-
1.4V
V
V
SS
G6
RUN 2
C8
+
OVSD
CLK1
Sync Detection
SYNCIN
OSC
CLK2SYNCOUT
G7
VREFOK Comparator
TFF
VCC
FREQ
TOO HIGH
+
ENABLE VREF
-
Q
START
SYNC
SYNC
IN
IFSET
IDSET
V
=5V
STOP
REF
C9
4.5
+
T1
-
FREQ
TOO LOW
G8
+
+
1.5V
A2
V
7.4/6.8V
V
OUT
V
OK
-
REF
V
DYLSET
FADJ
V5REF
+
0.13V
+
0.13V
RUN2
RAMP1
RAMP2
VFB1
V
FB2
Main PWM
Comparator
Aux.PWM
Comparator
2R
2R
R
-
-
R
RUN1
C11
C10
+
+
G9
GATE1
DRIVER
RSFF
RSFF
G10
Q
R
G12
G11
DRIVER
R
Q
GATE2
-
G13
DELAY
1.2V
F3
F4
-
S
S
Q
C12
+
+
C13
Reset
Dominant
+
Reset
Dominant
C14
Aux. Current
Limit Comparator
V
Main Current
Limit Comparator
-
RUN2
G14
G15
CLOCK
Skip Two
Clock Pulses
CLOCK
Skip2B
Skip2B
Skip Two
DRIVER
GATE2B
G16
Gnd
DELAY
G17
Clock Pulses
SET
SET
-
C15
-
+
+
1.7V
+
1.4V
C16
C17
+
-
V
Main 2nd Current
Threshold Comparator
Aux. 2nd Current
Threshold Comparator
V
ILIM1
I
LIM2
Theory of Application
ÔhighÕ, releasing GATE2 and GATE2B from their low state.
GATE2 and GATE2B begin switching according to condi-
tions set by the main control loop and the main regulated
output begins to rise. See startup waveforms in Figure 1.
Theory of Operation
Powering the IC
The IC has one supply, VCC, and one Ground lead. If VSS is
used for a bootstrapped supply the diode between VSS and
CC is forward biased, and the IC will derive its power
Soft Start
V
Soft start for the auxiliary power supply is accomplished
by placing a capacitor between OAOUT and Ground. The
error amplifier has 200µA of nominal of source current and
is ideal for setting up a Soft Start condition for the auxiliary
regulator. Care should be taken to make sure that the soft
start timing requirements are not in conflict with any tran-
sient load requirements for the auxiliary supply as large
capacitors on OAOUT will slow down the loop response.
Also, the Soft start capacitor must be chosen such that dur-
ing start or restart, both outputs will come into regulation
before the OUVDELAY timer trips. Soft Start for the main
supply is accomplished by charging soft start capacitor C6
through D5 and R7 at start up. After the main supply has
come into regulation C6 continues to charge and is discon-
nected from the feedback loop by D8.
from VSS. The internal logic monitors the supply voltage,
VCC. During abnormal operating conditions, all GATE
drivers are held in a low state. The CS5106 requires 1.5mA
nominal of startup current.
Startup
Assume the part is enabled and there are no over voltage
or under voltage faults present. Also, assume that all auxil-
iary and main regulated output voltages start at 0V. An
8V, Zener referenced supply is typically applied to VCC
.
When VCC exceeds 7.5V, the 5V reference is enabled and
the OSC begins switching. If the V5REF lead is not exces-
sively loaded such that V5REF < 4.5V nominal, ÔVREFOKÕ
goes ÔhighÕ and ÔRUN1Õ will go ÔhighÕ, releasing GATE1
from its low state. After GATE1 is released, it begins
switching according to conditions set by the auxiliary con-
trol loop and the auxiliary supply, VSS begins to rise.
When VSS > VCC + V(D1), P1 turns on and ÔRUN2Õ goes
8
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
