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CS51033YD8 参数 Datasheet PDF下载

CS51033YD8图片预览
型号: CS51033YD8
PDF下载: 下载PDF文件 查看货源
内容描述: 快PFET降压控制器不需要补偿 [Fast PFET Buck Controller Does Not Require Compensation]
分类和应用: 稳压器开关式稳压器或控制器电源电路开关式控制器光电二极管
文件页数/大小: 8 页 / 162 K
品牌: CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
 浏览型号CS51033YD8的Datasheet PDF文件第1页浏览型号CS51033YD8的Datasheet PDF文件第2页浏览型号CS51033YD8的Datasheet PDF文件第3页浏览型号CS51033YD8的Datasheet PDF文件第5页浏览型号CS51033YD8的Datasheet PDF文件第6页浏览型号CS51033YD8的Datasheet PDF文件第7页浏览型号CS51033YD8的Datasheet PDF文件第8页  
Block Diagram  
V
V
C
V
CC  
RG  
I
C
Oscillator  
Comparator  
V
GATE  
GATE  
C
OSC  
Flip-Flop  
A1  
7I  
G1  
R
Q
C
PGnd  
F2  
V
FB  
S
Q
G2  
Comparator  
V
-
FB  
A6  
2.5V  
1.5V  
1.25V  
+
0.7V  
V
CC  
+
Hold  
Off  
Comp  
V
CC  
-
-
Fault  
Comp  
1.15V  
+
G4  
CS Charge  
Sense  
Comparator  
G3  
I
A4  
T
CS  
Comparator  
CS  
2.3V  
A2  
R
Q
Q
F1  
I
I
T
T
5
55  
G5  
S
1.5V  
2.5V  
Slow Discharge  
Flip-Flop  
A3  
+
Slow Discharge  
Comparator  
2.4V  
Gnd  
Figure 1: Block Diagram for CS51033  
Circuit Description  
At startup, the voltage on all pins is zero. As VCC rises, the  
VC voltage along with the internal resistor RG keeps the  
PFET off. As VCC and VC continue to rise, the oscillator  
capacitor (COSC ) and the Soft start/Fault Timing capacitor  
(CS) charges via internal current sources. COSC gets charged  
by the current source IC and CS gets charged by the IT  
source combination described by:  
Theory of Operation  
Control Scheme  
The CS51033 monitors the output voltage to determine  
when to turn on the PFET. If VFB falls below the internal ref-  
erence voltage of 1.25V during the oscillator’s charge cycle,  
the PFET is turned on and remains on for the duration of the  
charge time. The PFET gets turned off and remains off dur-  
ing the oscillator’s discharge cycle time with the maximum  
duty cycle to 80%. It requires 7mV typical, and 20mV maxi-  
mum ripple on the VFB pin is required to operate. This  
method of control does not require any loop stability com-  
pensation.  
IT IT  
ICS = IT -  
+
(
)
55  
5
The internal Holdoff Comparator ensures that the external  
PFET is off until VCS > 0.7V preventing the GATE flip-flop  
(F2) from being set. This allows the oscillator to reach its  
operating frequency before enabling the drive output. Soft  
start is obtained by clamping the VFB comparator’s (A6) ref-  
erence input to approximately 1/2 of the voltage at the CS  
pin during startup, permitting the control loop and the out-  
put voltage to slowly increase. Once the CS pin charges  
above the Holdoff Comparator trip point of 0.7V, the low  
Startup  
The CS51033 has an externally programmable soft start fea-  
ture that allows the output voltage to come up slowly, pre-  
venting voltage overshoot on the output.  
4