Circuit Description: continued
100
The maximum duty cycle is set by the ratio of the on time,
ON, and the whole period, T = tON + tOFF. Because the
8
7
t
6
timing capacitor’s discharge current is trimmed, the maxi-
mum duty cycle is well defined. It is determined by the
ratio between the timing resistor RT and the timing capaci-
tor CT. Refer to figures 5 and 6 to select appropriate values
for RT and CT.
5
90
80
70
60
4
3
2
1. C = 47pF
2. C = 100pF
T
3. C = 150pF
T
T
1
fSW
=
; TSW = tCH + tDIS
TSW
4. C = 220pF
T
1
5. C = 390pF
T
6. C = 470pF
T
7. C = 560pF
T
8. C = 680pF
T
2500
2000
1500
1000
50
1
40
1. C = 47pF
T
5
10
15
20
25
30
35
(kΩ)
40
45
50
55
2. C = 100pF
T
R
T
3. C = 150pF
T
4. C = 220pF
T
5. C = 390pF
T
Figure 6: Duty Cycle vs. RT for Discrete Capacitor Values.
6. C = 470pF
T
7. C = 560pF
T
2
8. C = 680pF
T
3
4
500
5
6
7
8
0
5
10
15
20
25
30
35
40
45
50
R
T
(kΩ)
Figure 5: Frequency vs. RT for Discrete Capacitor Values.
8
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
