Package Pin Description: continued
PIN SYMBOL
PACKAGE PIN #
FUNCTION
16L PDIP & SO Narrow
7
RTCT
Timing resistor RT and capacitor CT determine oscillator frequen-
cy and maximum duty cycle, DMAX
.
8
ISET
Voltage at this pin sets pulse-by-pulse overcurrent threshold, and
second threshold (1.33 times higher) with Soft Start retrigger (hic-
cup mode).
9
VFB
Feedback voltage input. Connected to the error amplifier invert-
ing input.
10
11
COMP
SS
Error amplifier output. Frequency compensation network is usu-
ally connected between COMP and VFB pins.
Charging external capacitor restricts error amplifier output volt-
age during the start or fault conditions (hiccup).
12
13
LGnd
VREF
Logic ground.
5.0V reference voltage output.
14
VCC
Logic supply voltage.
15
16
PGnd
VC
Output power stage ground connection.
Output power stage supply voltage.
Block Diagram
VCC
VREF
Vcc_OK
START
STOP
V
= 5V
REF
-
+
LGnd
VREF_OK
VC
+
SLEEP
4.75V
200ns
4.3V
SYNC
RTCT
OSC
G
2
GATE
Q
S
R
D
F
4
ZD
1
1
SS
Clamp
G
13.5V
1
D
2
ISET
Clamp
COMP
VFB
PGnd
D
3
+
20k
2.5V
E/A
-
VREF
PWM
Comp
D
1
10k
VREF
55µA
VFB
Monitor
SS
53µA
+
–
SS
Monitor
G
4
2V
DISABLE
+
×
×
0.1V
SLOPE
4.7V
–
55ns
Blank
0.1
+
–
∑
I
SENSE
VISense
0.8
Q
2
2nd
Threshold
G
3
1.33
Discharge
Latch
FAULT
×
ISET
OV
VREF
12.5µA
UV
UV
Monitor
OV
Monitor
+
–
+
–
1.45V
2.5V
Figure 1: CS51021/22/23/24 Block Diagram
5
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
