Application Information: continued
exceeds ILIM, an internal latch is set and the output pulls
Sleep State
the gate of the MOSFET low for the remainder of the oscil-
lator cycle (fault mode). At the start of the next cycle, the
latch is reset and the IC reverts back to run mode until
another fault occurs. If a number of faults occur in a given
period of time, the IC “times out” and disables the MOS-
FET for a long period of time to let it cool off. This is
accomplished by charging the CFLT capacitor each time an
over current condition occurs. If a cycle goes by with no
overcurrent fault occurring, an even smaller amount of
charge will be removed from CFLT. If enough faults occur
together, eventually CFLT will charge up to 2.4V and the
fault latch will be set. The fault latch will not be reset until
CFLT discharges to 0.6V. This action will continue indefi-
nitely if the fault persists.
This device will enter into a low current mode (< 275µA)
when CTL lead is brought to less than 0.5V. All functions
are disabled in this mode, except for the regulator.
Inhibit
When the inhibit is greater than 2.5V the internal latch is
set and the external MOSFET will be turned off for the
remainder of the oscillator cycle. The latch is then reset at
the start of the next cycle.
Overvoltage Shutdown
The IC will disable the output during an overvoltage
event. This is a real time fault event and does not set the
internal latch and therefore is independent of the oscillator
timing (i.e. asynchronous). There is 325mV (typical) of
hysteresis on the overvoltage function. There is no under-
voltage lockout. The device will shutdown gracefully once
it runs out of headroom.
The off time and on time are set by the following:
2.4V - 0.6V
Off Time = CFLT
On Time = CFLT
×
4.5µA
2.4V - 0.6V
IAVG
×
Reverse Battery
where:
The CS4124 will not survive a reverse battery condition. A
series diode is required between the battery and the VCC
lead for reverse battery.
IAVG = (295.5µA × DC) - [4.5µA × (1 - DC)]
I
AVG = (300µA × DC) - 4.5µA
Load Dump
A 10Ω resistor, (RS) is placed in series with VCC to limit the
current into the IC during 40V peak transient conditions.
DC = PWM Duty Cycle
Boost Switch Mode Power Supply
The CS4124 has an integrated boost mode power supply
which charges the gate of the external high-side MOSFET
to greater than 5V above VCC. Three leads are used for
voltage boost. They are Boost, PMP and SNI. The PMP
lead is the collector of a darlington tied NPN power tran-
sistor. This device charges the inductor during its on time.
The boost lead is the input to chip from the external reser-
voir capacitor. The SNI lead is the emitter of the power
NPN and is connected externally to the RSNI resistor.
The power supply is controlled by the oscillator. At the
start of a cycle an R-S flip flop is set the internal power
NPN transistor is turned on and energy begins to build up
in the inductor. The RSNI resistor sets the peak current of
the inductor by tripping a comparator when the voltage
across the resistor is 450mV. The flip flop is reset and the
inductor delivers its stored energy to the load. The ripple
voltage (VRIPPLE) at the Boost lead is controlled by CBOOST
A snubber circuit, made up of a series resistor and capaci-
tor, is required to dampen the ringing of the inductor. A
.
value of 4Ω is recommended for RSNI
.
A zener diode is needed between the boost output voltage
and the battery. This will clamp the boost lead to a speci-
fied value above the battery to prevent damage to the IC.
A 9 volt zener diode is recommended.
1199
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
