Operating Description: continued
ter capacitor. Ceramic bypass capacitors (0.1µF) connected
Design Considerations
directly to VCC and VREF may be required to improve noise
filtering. They provide a low impedance path for filtering
the high frequency noise. All high current loops should be
kept as short as possible using heavy copper runs. The
error amp compensation circuitry and the converter out-
put voltage-divider should be located close to the IC and
as far as possible from the power switch and other noise
generating components.
High frequency circuit layout techniques are imperative to
prevent pulse-width jitter. This is usually caused by exces-
sive noise pick-up imposed on the current sense and volt-
age feed-back inputs. Noise immunity can be improved by
lowering circuit impedances at these points. The printed
circuit board layout should contain a ground plane with
low current signal and high current switch and output
grounds returning on separate paths back to the input fil-
Timing Diagram
SYNC
CT
Latch 1
“Set” Input
COMP
Sense
1
1
Latch 1
“Reset” Input
V
OUT
1
ENABLE
2
0V
Latch 2
“Set” Input
COMP
Sense
2
2
Latch 2
“Reset” Input
V
OUT
2
Applications Diagram
Dual Boost Regulator
V
IN
VCC
C
+
F1
5.0V
17V
Reference
Regulator
+
-
+
C
VREF
VCC
UVLO
F2
Internal
Bias
R
R
14V
+
-
2.5V
-
+
VREF
UVLO
3.4V
L
1
-
D
1
20kΩ
VOUT
1
Sync
+
+
COUT
1
L
2
Q1
VOUT
Oscillator
+
1
RT
CT
PWM
V
OUT
1
Latch 1
Current Sense
Comparator 1
RFB
1
D
2
2R
S
Q
R
+
VOUT
+
-
R
-
2
Sense
1
1.0mA
+
VFB
Error
Amp 1
COUT
1
RFB
R
2
2
0.5V
COMP
1
Sense
1
2
250µA
Q2
ENABLE
2
+
PWM
VOUT
V
OUT
2
Current Sense
Comparator 1
Latch 2
S
R
R
RFB
2R
Q
3
+
-
+
-
1.0mA
VFB
Error
Amp 2
R
2
0.5V
RFB
4
Sense
COMP
2
2
R
Sense
2
Gnd
Pwr Gnd
7
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
