Figure 3: Oscillator
cycle tends to exceed the maximum allowed, to prevent
transformer saturation in some power supplies, the inter-
nal oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of oscillator timing
components.
V
OSC
OSC
RESET
Setting the Oscillator
EA Output
The oscillator timing capacitor, CT, is charged by VREF
through RT and discharged by an internal current source
(Figure 3). During the discharge time, the internal clock
signal blanks out the output to the Low state, thus provid-
ing a user selected maximum duty cycle clamp.
Switch
Current
V
CC
Charge and discharge times are determined by the general
I
OUT
OUT
formulas:
V
VREF – Vlower
tc = RTCT ln
(
)
VREF – Vupper
Figure 2: Timing Diagram for key CS-384XB parameters
VREF – Id RT –Vlower
td = RTCT ln
VREF – Id RT – Vupper
(
)
VREF
Substituting in typical values for the parameters in the
above formulas:
RT
OSC
VREF = 5.0V, Vupper = 2.7V, Vlower = 1.0V, Id = 8.3mA,
then
CT
Gnd
tc ≈ 0.5534RTCT
2.3 – 0.0083 RT
td = RTCT ln
(
)
4.0 – 0.0083 RT
Vupper
The frequency and maximum duty cycle can be deter-
mined from the Typical Performance Characteristics
graphs.
Vlower
tc
td
Grounding
Sawtooth Mode
LARGE RT (≈10kΩ)
High peak currents associated with capacitive loads neces-
sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to ground in a single
point ground.
The transistor and 5kΩ potentiometer are used to sample
the oscillator waveform and apply an adjustable ramp to
Sense.
VOSC
Internal Clock
Triangular Mode
SMALL RT (≈700kΩ)
VREF
Internal Clock
Figure 3: Oscillator Timing Network and parameters
5
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
