Circuit Description: continued
former saturation in some power supplies, the internal
oscillator waveform provides the maximum duty cycle
clamp as programmed by the selection of oscillator com-
ponents.
V
OSC
OSC
RESET
Setting the Oscillator
Oscillator timing capacitor, CT, is charged by VREF through
RT and discharged by an internal current source. During
the discharge time, the internal clock signal blanks out the
output to the Low state, thus providing a user selected
maximum duty cycle clamp. Charge and discharge times
are determined by the formula:
EA Output
Switch
Current
V
CC
I
OUT
VREF - Vlower
tc = RTCT ln
V
OUT
(
)
VREF - Vupper
VREF - IdRT - Vlower
VREF - IdRT - Vupper
td = RTCT ln
Figure 2: Timing Diagram for key CS2841B parameters
(
)
Substituting in typical values for the parameters in the
above formulas:
VREF
VREF = 5.0V, Vupper = 2.7V, Vlower = 1.0V, Id = 8.3mA
RT
tc ≈ 0.5534RTCT
OSC
CT
2.3 - 0.0083 RT
4.0 - 0.0083 RT
td = RTCT ln
Gnd
(
)
The frequency and maximum duty cycle can be deter-
mined using the Typical Performance Characteristic
graphs.
Timing parameters
Vupper
Grounding
Vlower
High peak currents associated with capacitive loads neces-
sitate careful grounding techniques. Timing and bypass
capacitors should be connected close to Gnd pin in a sin-
gle point ground.
tc
td
Sawtooth Mode
LARGE RT (≈10kΩ)
The transistor and 5kΩ potentiometer, shown in the test
circuit, are used to sample the oscillator waveform and
apply an adjustable ramp to Sense.
VOSC
Internal Clock
Triangular Mode
SMALL RT (≈700kΩ)
VREF
Internal Clock
Figure 3: Oscillator Timing Network and parameters
5
CHERRY [ CHERRY SEMICONDUCTOR CORPORATION ]
