CEP730G/CEB730G
CEF730G
102
10
8
VDS=320V
ID=3.5A
RDS(ON)Limit
100µs
101
1ms
6
10ms
DC
4
100
2
TC=25 C
TJ=150 C
Single Pulse
10-1
0
100
101
102
103
0
4
8
12
16
Qg, Total Gate Charge (nC)
VDS, Drain-Source Voltage (V)
Figure 7. Gate Charge
Figure 8. Maximum Safe
Operating Area
VDD
on
t
toff
d(off)
t
r
t
d(on)
OUT
RL
t
f
t
VIN
90%
10%
90%
D
OUT
V
V
VGS
10%
INVERTED
RGEN
G
90%
50%
50%
S
IN
V
10%
PULSE WIDTH
Figure 10. Switching Waveforms
Figure 9. Switching Test Circuit
100
D=0.5
0.2
0.1
10-1
0.05
0.02
0.01
PDM
t1
t2
Single Pulse
10-2
1. Rθ JC (t)=r (t) * Rθ JC
2. Rθ JC=See Datasheet
3. TJM-TC = P* Rθ JC (t)
4. Duty Cycle, D=t1/t2
10-3
10-2
10-1
100
101
102
103
104
Square Wave Pulse Duration (msec)
Figure 11. Normalized Thermal Transient Impedance Curve
4
CET [ CHINO-EXCEL TECHNOLOGY ]
