CTM8B54E/55E/56E/57E
EPROM-Based 8-Bit CMOS Microcontroller
3.2 INSTRUCTION SET
Mnemonic
Operands
Instruction
Code
Status
Description
Cycles
Affected
BCR R, bit
BSR R, bit
Clear bit in R
Set bit in R
1
1
11 11bb brrr rrrr
11 10bb brrr rrrr
None
None
1 or
BTRSC R, bit Test bit in R and skip if clear
BTRSS R, bit Test bit in R and skip if set
11 01bb brrr rrrr
11 00bb brrr rrrr
None
None
2(skip)
1 or
2(skip)
CLRWDT
T0MODE
SLEEP
Clear Watchdog Timer
Load T0MODE Register
Go into standby mode
Load IOST Register
AND immediate with Acc
Exclusive OR immediate with Acc
Move immediate to Acc
Inclusive OR immediate with Acc
Return, place immediate in A
Call subroutine
1
1
1
1
1
1
1
1
2
2
2
1
1
1
1
1
1
1
1
1
1
01 0000 0000 0001
01 0000 0000 0010
01 0000 0000 0011
01 0000 0000 0rrr
00 1001 iiii iiii
00 1000 iiii iiii
00 0001 iiii iiii
00 0011 iiii iiii
00 1100 iiii iiii
10 0iii iiii iiii
10 1iii iiii iiii
01 0000 0000 0000
01 0000 1rrr rrrr
01 0010 drrr rrrr
01 0011 drrr rrrr
01 1110 drrr rrrr
01 1100 drrr rrrr
01 1101 drrr rrrr
01 0001 0000 0000
01 0001 1rrr rrrr
01 1000 drrr rrrr
TO, PD
None
TO, PD
None
Z
IOST R
ANDIA I
XORIA I
MOVIA I
IORIA I
Z
None
Z
RETIA I
LCALL I
LGOTO I
NOP
None
None
None
None
None
Z
Unconditional branch
No operation
MOVAR R
COMR R, d
MOVR R
RRR R, d
RLR R, d
Move Acc to R
Complement R
Move R
Z
Rotate right R
C
Rotate left R
C
SWAPR R, d Swap halves R
None
Z
CLRA
Clear Acc
Clear R
CLRR R
INCR R, d
Z
Increment R
Z
1 or
INCRSZ R, d Increment R, Skip if 0
01 1001 drrr rrrr
None
2(skip)
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Email: server@ceramate.com.tw
Tel:886-3-3529445
Fax:886-3-3521052
Http: www.ceramate.com.tw
Rev 1.1 Dec 26,2001
Page 7 of 23
CERAMATE [ CERAMATE TECHNICAL ]
