CTM8B54E/55E/56E/57E
EPROM-Based 8-Bit CMOS Microcontroller
Mnemonic
Operands
Instruction
Code
Status
Affected
Description
Cycles
DECR R, d
Decrement R
1
01 0110 drrr rrrr Z
1 or
DECRSZ R, d Decrement R, Skip if 0
01 0111 drrr rrrr None
2(skip)
SUBAR R, d
XORAR R, d
ANDAR R, d
ADDAR R, d
IORAR R, d
Subtract Acc from R
Exclusive OR Acc with R
AND Acc with R
1
1
1
1
1
01 1010 drrr rrrr C, DC, Z
01 1011 drrr rrrr Z
01 0100 drrr rrrr Z
Add Acc and R
01 0101 drrr rrrr C, DC, Z
01 1111 drrr rrrr Z
Inclusive OR Acc with R
Note:
b : Bit position
WDT : Watchdog Timer
R : Register address
i : Immediate data
PD : Power down flag
Z : Zero flag
Acc : Accumulator
TO : Time overflow bit
C : Carry flag
T0MODE : T0MODE register
IOST : I/O port status register
DC : Digital carry flag
I : (i7i6i5i4i3i2i1i0)
R : (r6r5r4r3r2r1r0)
d Î [0, 1]
:Destination
If d is “0”, the result is stored in the Acc register.
If d is “1”, the result is stored back in register R.
3.3 I/O PORTS EQUIVALENT CIRCUIT
D
Q
Acc Data
VDD
IOST
Latch
CK
QB
QB
I/O Pin
IOST R
D
Data Bus
VSS
Data
Latch
CK
Q
WR Port
RD Port
Note : 1. The IOST registers are “write-only” and set upon RESET.
2. If the IOST latch is “0”, the corresponding I/O pin is in output mode;
if the IOST latch is “1”, the corresponding I/O pin is in input mode.
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN, R.O.C
Tel:886-3-3529445
Fax:886-3-3521052
Email: server@ceramate.com.tw
Http: www.ceramate.com.tw
Rev 1.1 Dec 26,2001
Page 8 of 23
CERAMATE [ CERAMATE TECHNICAL ]
