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CP494 参数 Datasheet PDF下载

CP494图片预览
型号: CP494
PDF下载: 下载PDF文件 查看货源
内容描述: 开关模式脉宽调制控制电路 [SWITCHMODE Pulse Width Modulation Control Circuit]
分类和应用: 开关
文件页数/大小: 11 页 / 155 K
品牌: CERAMATE [ CERAMATE TECHNICAL ]
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CP494  
SWITCHMODE Pulse Width Modulation Control Circuit  
APPLICATIONS INFORMATION  
Description  
common mode input range from –0.3 V to (V – 2V), and  
CC  
The CP494 is a fixed–frequency pulse width modulation  
control circuit, incorporating the primary building blocks  
required for the control of a switching power supply. (See  
Figure 1.) An internal–linear sawtooth oscillator is  
may be used to sense power–supply output voltage and  
current. The error–amplifier outputs are active high and are  
ORed together at the noninverting input of the pulse–width  
modulator comparator. With this configuration, the  
amplifier that demands minimum output on time, dominates  
control of the loop.  
frequency– programmable by two external components, R  
T
and C . The approximate oscillator frequency is determined  
T
by:  
When capacitor C is discharged, a positive pulse is  
T
generated on the output of the deadtime comparator, which  
clocks the pulse–steering flip–flop and inhibits the output  
transistors, Q1 and Q2. With the output–control connected  
to the reference line, the pulse–steering flip–flop directs the  
modulated pulses to each of the two output transistors  
alternately for push–pull operation. The output frequency is  
equal to half that of the oscillator. Output drive can also be  
taken from Q1 or Q2, when single–ended operation with a  
maximum on–time of less than 50% is required. This is  
desirable when the output transformer has a ringback  
winding with a catch diode used for snubbing. When higher  
output–drive currents are required for single–ended  
operation, Q1 and Q2 may be connected in parallel, and the  
output–mode pin must be tied to ground to disable the  
flip–flop. The output frequency will now be equal to that of  
the oscillator.  
1.1  
RT CT  
fosc  
For more information refer to Figure 3.  
Output pulse width modulation is accomplished by  
comparison of the positive sawtooth waveform across  
capacitor C to either of two control signals. The NOR gates,  
T
which drive output transistors Q1 and Q2, are enabled only  
when the flip–flop clock–input line is in its low state. This  
happens only during that portion of time when the sawtooth  
voltage is greater than the control signals. Therefore, an  
increase in control–signal amplitude causes a corresponding  
linear decrease of output pulse width. (Refer to the Timing  
Diagram shown in Figure 2.)  
The control signals are external inputs that can be fed into  
the deadtime control, the error amplifier inputs, or the  
feedback input. The deadtime control comparator has an  
effective 120 mV input offset which limits the minimum  
output deadtime to approximately the first 4% of the  
sawtooth–cycle time. This would result in a maximum duty  
cycle on a given output of 96% with the output control  
grounded, and 48% with it connected to the reference line.  
Additional deadtime may be imposed on the output by  
setting the deadtime–control input to a fixed voltage,  
ranging between 0 V to 3.3 V.  
The CP494 has an internal 5.0 V reference capable of  
sourcing up to 10 mA of load current for external bias  
circuits. The reference has an internal accuracy of $5.0%  
with a typical thermal drift of less than 50 mV over an  
operating temperature range of 0° to 70°C.  
500 k  
V
CC  
= 15 V  
C = 0.001 mF  
T
100 k  
10 k  
Functional Table  
0.01 mF  
0.1 mF  
fout  
fosc  
Input/Output  
Controls  
Output Function  
=
Grounded  
Single–ended PWM @ Q1 and Q2  
Push–pull Operation  
1.0  
0.5  
@ V  
ref  
1.0 k  
500  
The pulse width modulator comparator provides a means  
for the error amplifiers to adjust the output pulse width from  
the maximum percent on–time, established by the deadtime  
control input, down to zero, as the voltage at the feedback  
pin varies from 0.5 V to 3.5 V. Both error amplifiers have a  
1.0 k 2.0 k 5.0 k 10 k 20 k 50 k  
100 k 200 k 500 k 1.0 M  
R TIMING RESISTANCE (W)  
T,  
Figure 3. Oscillator Frequency versus  
Timing Resistance  
* All specs and applications shown above subject to change without prior notice.  
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN  
Tel:886-3-3214525  
Email: server@ceramate.com.tw  
Http: www.ceramate.com.tw  
Rev 1.0 Apr.19,2004  
Page 5 of 11  
Fax:886-3-3521052