24LLC02
2K-Bits Serial EEPROM For Low Power
Master
SCL Line
Bit 1
Bit 9
Data from
Transmitter
ACK from
Receiver
ACK
Figure 1-8. Acknowledge Response From Receiver
·
Slave Address : After the master initiates a Start condition, it must output the address of the device to be
accessed. The most significant four bits of the slave address are called the “device identifier”. The identifier
for the 24LLC02 is “1010B”. The next three bits comprise the address of a specific device. The device
address is defined by the state of the A0, A1 and A2 pins. Using this addressing scheme, you can cascade
up to eight 24LLC02 on the bus (see Table 1-2 below).are used by the master to select which of the blocks
of internal memory (1 block= 256 words) are to be accessed. The bits are in effect the most significant bits
of the word address.
·
Read/Write : The final (eighth) bit of the slave address defines the type of operation to be performed. If the
R /W bit is “1”, a read operation is executed. If it is “0”, a write operation is executed.
Table 1-2. Slave Device Addressing
Device
Device Identifier
Device Address
R/ W Bit
b0
b7
1
b6
0
b5
1
b4
0
b3
A2
b2
A1
b1
A0
24LLC02
R/ W
NOTE: The B2, B1, B0 correspond to the MSB of the memory array address word.
* All specs and applications shown above subject to change without prior notice.
1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN
Tel:886-3-3214525
Email: server@ceramate.com.tw
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Rev 1.0 Dec. 26, 2001
Page 7 of 19
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